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It would be awesome if the SaxonSoC supported the [Tomu FPGA (Fomu)](https://fomu.im). This would be an awesome introduction into to pure SpinalHDL design.
Happy to send people boards.
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Trying to migrate my hobby project SoC from VexRiscv to VexiiRiscv. I suspect there is a bug in FetchL1Plugic:
After fetching first few commands FetchL1Plugin produces unknown (`'xxxx`) output if c…
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SpinalHDL can neither add macro definition to Verilog source nor add flags when invoking Xsim.
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In SpinalSim we now have the capability to interact with buses like AXI to read bits from the design. My design currently exposes some SpinalHDL `Bundle`, `Union` and `SpinalEnum` over AXI and the si…
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@Dolu1990 convinced me that even if SpinalHDL enables the user to abstract the wires, sometimes the user wants to manipulate wire-by-wire so aligning stuff would be great.
In https://github.com/num…
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I want a document on how to use it，thank you!
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hi, i notice that when adding a user-defined interrupt using UserInterruptPlugin, it just use the `interruptPending` as the cond signal ,without any enable signal as a gate controller https://githu…
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The earlylast argument is not available in the `StreamFragmentWidthAdapter`'s `make` methods
https://github.com/SpinalHDL/SpinalHDL/blob/2527c7c6b0fb0f95e5e1a5722a0be732b364ce43/lib/src/main/scala/…
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Hardware :
- Board : https://www.efinixinc.com/products-devkits-titaniumti375c529.html
- HDMI : https://www.digikey.com/en/products/detail/efinix-inc/EFX-HDMI/17084519?s=N4IgTCBcDaIKYDMCWA7JAPABACw…
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I am wondering how can i integrate these both part of code which are in different location
NaxRiscv/src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala
https://github.com/SpinalHDL/NaxRis…