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## Prerequisites
Currently the synthesis tests are only run with Vivado_HLS. We should add Quartus and Vitis synthesis tests
### Motivation
We should test all the backends we support.
### Part…
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When I try to process a test entity instantiating a `scfifo` from the `altera_mf` library I get this error.
ERROR LOG:
```
ghdl --std=08 -P=altera/ -fsynopsys test.vhdl -e test
1. Executing GHD…
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Currently, the method for programming the FPGA on the Arduino Vidor is:
1. Use Intel Quartus to do the FPGA development
2. Obtain a bitstream
3. Paste the bistream into the header of a specific Ard…
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Hello,
I tried to setup PoC as described in the Quickstart Guide in the readme. After experiencing the bug described in #62 and applying the suggested fix (renaming PoC.py in the submodule) the fol…
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Hi,
great work, thank you.
I would like to give it a try for my own 65C02 homebrew computer I‘m about to assemble.
But I‘m a bit lost regarding the EPM7128.
Would you please explain how to pr…
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maybe add .gitignore rules?
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I have tested this code on esp32 and when I try to upload the code it shows "line 421: Allocating memory failed." on the web page... The svf file is generated using 'Quartus 2'
[op.zip](https://githu…
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Hello! @Dolu1990, I know you previously answered a similar question on issue #22. I running into the same error on the DE1-SOC which uses a Cyclone V chip. My confusion comes from the fact that you ha…
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- [x] #107
- [x] Figure out how to get Quartus to produce Verilog as output (why is not a default??) (answer: `quartus_cdb mult_0_stage_signed_8_bit --vqm=tmp`)
- [ ] #106
- [ ] #105
- [x] #8…
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Hi,
I am trying litex to generate a rocket based soc for terrasic de2 115.
Command i used to build is:
`litex-boards/litex_boards/targets/terasic_de2_115.py --build --cpu-type rocket --cpu-va…