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Seeking further clarification on [this behavior](https://github.com/alexforencich/verilog-axi/issues/19)
If `len = 50`, and if axis stream packet only has 40 words (tlast raised after sending 40 b…
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Hi,dear dolu,
I am currently learning how to use the kernel generated by Litex to run the dhrystone algorithm on SOC. The specific operation is: 1. Generate a SOC system with a Nax core, and then bas…
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您好!
在生成XSTop.v文件以后,我想简单的仿真下,就只是给了时钟和复位。如下所示:
XSTop XSTop_inst
(
.io_clock ( sys_clk ),
.io_reset ( !sys_rst_n ),
//io_sram_config,
//input …
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Hi it seems the changes needed for 2021-2023 is minor.
```
diff --git a/examples/alpha250/adc-dac-dma/block_design.tcl b/examples/alpha250/adc-dac-dma/block_design.tcl
index e28f2090..edb64099 10…
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command: make SUB_PROJECT=constellation BINARY=none CONFIG=AXI4TestConfig00 run-binary-debug
simulator: verilator
error log:
Exception in thread "main" java.lang.reflect.InvocationTargetException…
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### Is your feature request related to a problem? Please describe.
I need to align objects in a cube like pattern and object grid aligner only has row and column axis
### Describe the solution you'd…
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Hello,
I am currently working on utilizing the Axi DMA module through PYNQ. I have created an HLS Axi Lite module that allows me to control the Axi DMA IP module using wires. However, whenever I at…
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I recently took an opportunity to review [mkFabric_AXI4.v](https://github.com/bluespec/Piccolo/blob/master/builds/RV32ACIMU_Piccolo_verilator/Verilog_RTL/mkFabric_AXI4.v) using a formal AXI4 property …
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请问当XDMA设定成AXI-Stream mode时, c++host software 如何撰写?