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I'm guessing it might be the HUB (see dmesg from below), I'll see if I can find some USB C device, that doesn't need the HUB
```py
#!/usr/bin/env python3
#
# This file is part of Facedancer.
#
…
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Hello. Not sure if the right place to ask, but here I go:
been trying to flash a rust program to my ecp5 fpga (colorlight 5a-75e). however when booting, im not getting the expected output.
```rs
…
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Hi,
I have been trying to do the SoC example for the Arty A7 and I had a problem when it is the time to add the .bram_tcm file. My doubt is how it is possible to attach the software file in the sy…
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I'm trying to understand FPGA-shells so I can add a PCIe to my SoC in Chipyard, but I was also thinking of adding SPI flash. While digging through VCU118NewShell.scala I saw that `//SPI Flash not func…
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I'd like to get a list together of all the current documentation, guides and example code to learn the basics of FPGAs and how they compare to developing on something like an Arduino.
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Hi all, our lab has only a soc xilinx zcu102 and i'm a freshman of FPGA developing. I want to verify zynqnet on zcu102 so i have to transplant it from 7045 to zcu102. Are there any docs or other proje…
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Hello, i want to simulate llama llm (the version on c++ that there is an option to cross compile it and simulate the riscv edition with vector extension) on ara. I successfully installed all the tool…
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This error occurs when executing Cologne Chips place and route 'p_r' in step08 and step10 only.
**Observed error output details:**
```
home/fm/cc-toolchain-linux/bin/p_r/p_r -i SOC_synth.v -o SO…
fm4dd updated
10 months ago
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Trying to port this to 20.1 toolchain, using hints from cyclone5 dev kit instructions. I am able to get the sof and uboot compiled and working, but I am having problems with the linux kernel devicetre…
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**Problem Statement**:
In eFPGA device, IO interface consists of input/output buffers (registered/non-registered) unlike fixed FPGA which has inpad/outpad connected to some kind of GPIO. Each IO inte…