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This is the first RISCV core I've been able to get up and running without breaking my head. Much appreciation for the SpinalHDL team for the making this work with Qsys and Avalon. :) (Although SpinalH…
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Hi Charles,
Following on from my previous issue https://github.com/SpinalHDL/NaxRiscv/issues/70#issuecomment-1910747595, where I had an error with the double and float tests using RVLS.
I didn'…
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In the current implementation the `user` signal in `Axi4StreamBundle` is defined to be `dataWidth * userWidth`:
https://github.com/SpinalHDL/SpinalHDL/blob/ef0063da38424830a5b29f188e3887e2b043cb75/…
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Hi, I have a module written in VHDL which has an Axi4 interface and I would like to interface it with the Axi4 class of the SpinalHDL so I can use it inside the Vex. My question is: what are the steps…
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Currently I am developing against a local SpinalHDL `dev` branch, along with local VexRiscv `dev` and the VexRiscv-specific latest OpenOCD (i.e. using the "old" VexRiscv debug module") and I am seeing…
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Trying to migrate my hobby project SoC from VexRiscv to VexiiRiscv. I suspect there is a bug in FetchL1Plugic:
After fetching first few commands FetchL1Plugin produces unknown (`'xxxx`) output if c…
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The goal is to both:
* Make it easier for all people discovering SpinalHDL (knowing VHDL and Verilog might help but it is not a requirement)
* Make it easier for people to find information
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I notice the csignals lookup table has incorrect definition of the op1sel and op2sel signals:
`JALR -> List(Y, BR_JR , OP1_RS1, OP2_IMI , ALU_X , WB_PC4, REN_1, MEN_0, M_X , MT_X, CSR.N),
…
ZiCog updated
6 years ago
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Dear charles,
How you recommend me to compile the updated code with
```
sbt "runMain naxriscv.Gen64"
```
like which branch to stay in spinal HDL and which branch to stay in main one ?
…
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Hi,
I've been working with SpinalHDL for a few months and am inspired by the design of NaxRiscv. I aim to deepen my understanding by building a toy CPU from scratch. While I appreciate the complexi…