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Hello,
I want to synthesize two simple modules, the (Verilog) file the top module instantiates the VHDL module twice. I am unable to synthesize it. Help me figure other this problem how I can solve…
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I'm comparing two netlists through equiv_make given as below:
**First netlist:**
```
module inverter(in, out);
input in;
wire in;
output out;
wire out;
sky130_fd_sc_hd__inv_2 0 (
.A(in),
.…
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the included `lef` for `user_proj_example` is for sky130, so running `make harden` which happens to build `user_project_wrapper` first using the old lef results in the following error:
```
[ERROR]…
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### Description
Hi, I am trying to harden a small eFPGA (4 x 4 CLB), I have used OpenFPGA to create the FPGA architecture.
This FPGA has basic modules like CLB, switching blocks, and connection bloc…
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**Describe the bug**
When following the instructions in `README.md`, I ran `make pdk` followed by `make install`. The `make install` failed.
**Version**
5ad1db95a80e04c541bf16d59678375a60734807
…
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**Describe the bug**
I'm running testbenches with sky130 architecture files. When I synthesize a fabric and benchmarks for it, preconfigured testbenches are successfully runned. However when I run fu…
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**Describe the bug**
Trying to run the installation as detailed in the documentation. I raised an issue about this yesterday and was said to be solved, but I am having issues still with OpenRAM or Co…
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When trying to import some sky130 gate level verilog, bigspicy fails with:
```
NotImplementedError: Is this supposed to be a disconnection?
```
The problem is a tie cell, in which a disconnect…
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```python
File /laygo2_workspace_sky130/laygo2_example/logic/inv.py:105
102 print("")
104 # Uncomment for BAG export
--> 105 laygo2.interface.magic.export(lib, filename=ref_dir_MAG_exporte…
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### Description
In `libs.tech/openlane/config.tcl` following configuration should be updated.
```
set ::env(GPIO_PADS_VERILOG) "\
$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/verilog/sky130…