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Hi,
I'm trying to test the SoC on a Nexys Video FPGA. When I try to run OpenOCD after loading the bitstream to the FPGA, the following error occurs:
```
ivantaka@ivantaka-pc:~$ sudo $OPENOCD/bi…
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Hi everyone,
I have a dubs about the regeneration process of the Verilog of the VexRiscV core, in particular I trying to modify the core inside the pythondata-cpu-vexriscv_smp repository and adding…
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Hi,
Deploying a design which is ~ 60k lut on Digilent nexys video, the sys_rst timings are getting worst and worst.
Seems like using the FPGA regular interconnect to wire sys_rst everywere isn't g…
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Running nextpnr-xilinx version `Version 0.6.0-1-g55beb766` for part `xc7a200tsbg484-1`
I'm trying to file an issue for nextpnr-xilinx failing to handle my yosys output. Along the way, I found out t…
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Hi,
I update Litex and tested NaxRiscv, but it seems that #1817 did break something related to the peripheral interconnect.
UART work enough for the bootloader, but both spi and mmc are broken (…
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I tried
python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=naxriscv --with-video-framebuffer --with-sdcard --build --load
but i get this error
OSError: Unable to find or sour…
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I am currently trying to synthesize a project (same constraints and project file given in my previous issue (#15).
When invoking `./build/nextpnr-xilinx --chipdb nexys.bin --json ~/p/dragon/build-…
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Hi every one,
I ported rvfpga to nexys video board. I can program FPGA by vscode platformio and LEDs blinks 3 times. So the risc-v is alive.
The platformio.ini is:
```
[env:swervolf_nexys]
pl…
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Hi, currently testing stuff with the following config :
AXI4 64 bits -> digilent nexys video DDR (16 bits physical, 128 bits access bus)
Things seems to mess up between lower and upper 64 bits of…
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Hi, I'm currently working on a final project for my Verilog class that outputs to a VGA monitor. I already have a basic VGA signal generator module that outputs 640x480, but I don't want to keep gener…