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### Version
Yosys 0.38+92 (git sha1 f7737a12c, clang++ 11.1.0 -fPIC -Os)
### On which OS did this happen?
macOS
### Reproduction Steps
```
read_verilog -sv
povik updated
5 months ago
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When running simulation on the top_sim.v of Tut-5 on verification of neural network, I encountered the following error:
```
$readmemb(fileName, config_mem);
```
Error: first argum…
qcsui updated
7 months ago
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Here is a patch that will allow the boot loader to synthesize with Yosys. All of the changes are simple, and allow the RTL to pass Yosys rather strict syntax (parameter, assignment) and topology chec…
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Icarus Verilog does not support the System Verilog used in the [fx68k](https://github.com/ijor/fx68k) M68000 open source core.
It seems like these two features are missing:
1. Support top level …
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Hi!
Multiple packed array dimensions are system verilog feature. Yet following code compiles fine with -g2005 flag.
```verilog
module test(input [3:0][7:0] i, output [31:0] q);
assign q …
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Since merging code related to pull request #59, netgen no longer correctly handles implicit pins in verilog. This issue is caused by the fact that verilog syntax allows pins to be missing from a modu…
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## Steps to reproduce the issue
Hi, I noticed the following miscompilation bug. Not sure if it is considered interesting or not:
Consider the following Verilog program:
```
> cat small.v
mo…
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### Motivation
I'm wondering if we can have a helper function to save system Verilog module `generateSynth()` to a file. Its a pain to keep copy pasting the code below to keep track of system verilog…
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If the intent was to follow the standard used by the sky130 PDK, then this is an epic fail. It needs correcting on multiple fronts.
For starters, the standard cell verilog modules make references …
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Even with inlining, we have bloat of wires in output verilog. See a simple add:
magma:
```python
Top = m.DefineCircuit("Top", "I0", m.In(m.UInt(8)), "I1", m.In(m.UInt(8)), "O", m.Out(m.UInt(8)))
…