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Hello Zcashers! I am the co-founder of [Bitseed](https://bitseed.org/), a project with a mission to make it easy for anyone to run their own bitcoin full node. In the past we have experimented with al…
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Type: Bug
I cannot access servers with ssh.
VS Code version: Code 1.89.1 (dc96b837cf6bb4af9cd736aa3af08cf8279f7685, 2024-05-07T05:16:23.416Z)
OS version: Linux x64 5.15.0-102-generic snap
Modes:
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### Description:
Incorporating a basic error detection mechanism. This feature will initially focus on identifying common syntax errors within user-provided SystemVerilog code. By doing so, it will p…
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Most modules have one pair of clock and reset only so we can omit spacyfying clock and reset singals on `always_ff` blocks.
```systemverilog
always_ff {
if_reset {
q = 0;
} else {
…
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ao68000.v line 2841 shows result assigned with a non-blocking assignment.
a068000.v line 2852 shows result assigned with a blocking assignment.
I don't know what that the Altera synthesizer does wit…
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Are you planning on implementing elaboration as well. Is the ultimate goal to output a synthesizable design? Os is that outside the scope of this project?
> 1364-2005: Elaboration is the process th…
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I have taken a quick look into supporting the Synopsys VCS simulator.
It looks like similar to Cadence's `cds.lib`, VCS needs a file `.synopsys_vss.setup` for the library name-to-path mapping. http://…
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If the idea is to create an enhanced version of docco, why not get rid of pygments in favor of something that does not need to be installed, such as prismjs.com
This way users would need one less ste…
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It would be awesome if the standard SystemVerilog assert syntax was supported.
```verilog
// currently not supported
assert( l_c === 1'b0 );
// current work-around
if( l_c === 1'b0 ) ; el…
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Hello,
I want to ask if the compiler has the ability to extract the parameter name instead of turning them into constant after compiler. For the below example:
```
addrmap test#(bit BASE_ADDR_C…