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Using prebuilt verible-v0.0-383-g0b0011b binaries, it looks like `verilog_syntax: parse-as-class-body` doesn't work because it complains about "non-class functions":
```
$ cat bar.svh
// verilog_sy…
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Hi!
Multiple packed array dimensions are system verilog feature. Yet following code compiles fine with -g2005 flag.
```verilog
module test(input [3:0][7:0] i, output [31:0] q);
assign q …
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#### Expected Behaviour
`--enable_timing_computations option` enabled disabling of timing calculations.
#### Current Behaviour
Flag is now removed.
#### Context
`--enable_timing_computa…
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When I try to compile J1B (via `make` in `j1b/swapforth/j1b/verilator`), I get the old error:
```
verilator --l2-name v -Wall -I../verilog/ --cc j1b.v ../verilog/j1.v ../verilog/stack.v --top-modul…
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[Enter steps to reproduce:]
1. ...
2. ...
**Atom**: 1.50.0 x64
**Electron**: 5.0.13
**OS**: Mac OS X 10.15.6
**Thrown From**: [language-systemverilog](https://github.com/pistoletpierre/langu…
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### Version
Yosys 0.26+50 (git sha1 0f2d226ae, gcc 7.5.0-3ubuntu1~18.04 -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
1. download verilog files: https://githu…
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After we come closer to the System SBOM, we should also have HBOM in mind.
It can also cover topics like VHDL and Verilog elements.
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### Version
Yosys 0.39+149
### On which OS did this happen?
Linux
### Reproduction Steps
I inadvertently created a design with a syntax error：
![image](https://github.com/YosysHQ/yosys/assets/5…
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It seems that the iverilog invocation doesn't allow for SystemVerilog support:
https://github.com/google/xls/blob/c330e64365e56439ab9496159aa8664c6cd5eb6a/xls/simulation/simulators/iverilog_simulator…
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yield statements seem like wait or join in Verilog.
I would like for Cocotb has more functionalities for event-waiting.
Systemverilog has three different kinds of join keywords, join, join_any, and j…