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I use `buildroot of ariane-sdk` build image,
and i want to mount `rootfs.tar.xz of lowrsic` as real rootfs.
i modify init script of initramfs:
![init_script](https://user-images.githubusercontent.c…
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### Discussed in https://github.com/Xilinx/finn/discussions/932
Originally posted by **Madhurima8** December 3, 2023
I am facing an issue while installing FINN with docker. when I ran this co…
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Hi,
I am doing the verification of cva6.
I want to know how start address is generating or assigned as per the linkers script inside verif/tests/.
May I know how to modify or change the start ad…
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The scheduler ISR which drives the full `v1` code now has two possible sources:
1. Existing method: time-based ISR which is arbitrarily configurable to any sample rate (defaults to 10 kHz), and is NO…
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### Motivation :
MIGraphX can support multiple backend targets. It fully supports GPU target currently. It can target the CPU backend with limited functionality and FPGA support is in the BETA mod…
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## Brief summary of issue
So we have seen that we have an issue with the sbit mapping in V3 electronics. This issue persists when using GEBv3c+OHv3c hardware:
- Using a OHv3c+GEBv3b: http://c…
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# 总结
- https://github.com/cisen/sourcecode-verilog-ethernet-00
- [以太网数据帧](https://github.com/cisen/blog/issues/955)
- http://www.360doc.com/content/12/0425/13/6973384_206409204.shtml
- PHY又分为物理介质相…
cisen updated
3 years ago
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
I have an error while generating the FPGA bitstream:
```bash
make fpga
```
Gi…
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**For Vivado questions, please use [Vivado forum](
https://forums.xilinx.com/t5/Vivado-RTL-Development/ct-p/DESIGN)**
**For Vitis questions, please use [the Vitis forum](
https://forums.xilinx.co…
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LE: see my next reply first
I can't seem to be able to run the hello_world example and I'm not sure what I'm holding wrong here.
Issues here don't seem to hit anything on the topic (or maybe I'm s…