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Hello!
After using the synthesis tool for generating the C code for the RISC-V processor, there are make build errors while further flashing the code on the MAX78000EVKIT board using VS Code.
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When trying to build for esp32c3(or any riscv processor based esp32) tiny_types.c and tiny_types.h don't include the esp32/esp32_hal.inl(or .h, I don't remember).
This can be fixed by adding to the l…
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This project seeks a set of Ghidra import regression tests to validate sensible behavior after importing executable binaries into new versions of Ghidra. It's morphed somewhat into generating newer e…
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By the way,where can I get trainning about chisel develop for AXI, DMA,SRAM ,etc.
Thanks
TDppy updated
4 months ago
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Respected sir
I am working on Oracle virtual box with Ubuntu 22.04 LTS version
1. I ran the prerequisite dependency commands which gave some 404 error but was overcome using the --fix-missing
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Hi there, as I can see current riscv profile is mainly for application processor, and there is not yet a profile targeting at mcu market, maybe a mcu profile could be set, for mcu, interrupt should be…
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I am trying to call sim_t function from spike.cc , in my cpp(c++) wrapper API (provided riscv-isa-sim build as input for compilation) to create shared object, which I will call in System verilog (SV) …
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Hello,
I am encountering an issue when I used nx_packet_allocate because ULONG is considered to be 8 bytes for the RISCV-64 bits architecture.
It worked perfectly on my previous target CORTEX-R4…
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On https://github.com/SymbioticEDA/riscv-formal there's a Table of Contents that gives good information, but I have a new RISC-V CPU I want to try to test and need to know the procedure to create a fo…
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**Describe the bug**
The checkpoints are malfunctioning.
**Affects version**
Commit bae34876780dfb2bc22b9151bfda1d39ee80cfb1 (HEAD -> stable, tag: v23.1.0.0, origin/stable, origin/HEAD)
**gem5…