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JulianKemmerer
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PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
https://github.com/JulianKemmerer/PipelineC/wiki
GNU General Public License v3.0
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changed dict() to {}
#160
ghost
closed
1 year ago
0
WIP: CHG: Use pycparser as a git submodule
#159
AlexLao512
opened
1 year ago
21
WIP: CHG: Move pipelinec specific headers into sub-directory
#158
AlexLao512
closed
1 year ago
2
CHG: Move configuration files
#157
AlexLao512
closed
1 year ago
1
DOC: Move images into sub-directory
#156
AlexLao512
closed
1 year ago
0
cleaned up utilities.py
#155
ghost
closed
1 year ago
4
updated pyproject.toml
#154
ghost
closed
1 year ago
0
Updating code to follow more modern style
#153
ghost
closed
1 year ago
3
1024x768 resolution
#152
suarezvictor
closed
1 year ago
3
celing rounding in coarse slicing
#151
suarezvictor
closed
1 year ago
5
force pipeline stages in for loops
#150
suarezvictor
closed
2 weeks ago
2
Default zero initialized arrays can generate broken VHDL syntax when indexed by constants
#149
JulianKemmerer
closed
1 year ago
1
Global variables of compound types cannot be driven from multiple main functions
#148
JulianKemmerer
opened
2 years ago
0
Raw VHDL interface should be bits per stage not slices
#147
JulianKemmerer
closed
2 weeks ago
1
Static local variables cannot be declared inside IFs
#146
JulianKemmerer
opened
2 years ago
0
Make cache of pipelined basic operations
#145
JulianKemmerer
closed
2 years ago
3
Starting device models code...
#144
JulianKemmerer
closed
2 years ago
0
add script to parse and estimate delays of unary and binary operations
#143
suarezvictor
closed
2 years ago
11
FIFO_FWFT implementation causes output to pause unexpectedly long after flow control assertion
#142
JulianKemmerer
opened
2 years ago
2
Added gui-hw-emu option to xrt.ini, so user can see Vivado generated …
#141
bartokon
closed
2 years ago
0
Test axis stream with fifo
#140
bartokon
closed
2 years ago
0
Loop iterators must be declared outside of the loop
#139
JulianKemmerer
opened
2 years ago
0
Allowing global variables to be marked as top level clock inputs
#138
JulianKemmerer
opened
2 years ago
0
User generated clock wires top level connections are not recognized by all timing tools
#137
JulianKemmerer
opened
2 years ago
2
Copy IEEE proposed vhdl package files to output dir as needed
#136
JulianKemmerer
closed
2 years ago
1
Update for Vitis 2022.2
#135
bartokon
closed
2 years ago
0
Reconsider assumption that all 2:1 muxes will have same path delay
#134
JulianKemmerer
opened
2 years ago
0
First autopipelining run for new FPGA part synthesizes muxes repeatedly
#133
JulianKemmerer
opened
2 years ago
0
Allow input pointer arguments to be used for output ports
#132
JulianKemmerer
opened
2 years ago
0
Vivado 2022.2 does not need fixed_pkg_2008 compiled
#131
JulianKemmerer
closed
2 years ago
2
Flatten top level output structs when rending VHDL - most tools dont allow complex types at the top level
#130
JulianKemmerer
opened
2 years ago
0
Function, type, variable, etc names must not conflict with C and VHDL reserved words
#129
JulianKemmerer
opened
2 years ago
2
Structs must use typedef tag_name == struct_alias for struct definitions
#128
JulianKemmerer
opened
2 years ago
0
Vitis import example
#127
bartokon
closed
2 years ago
7
Clean and standardize PipelineC repo.
#126
bartokon
closed
1 week ago
4
Generating output using `--verilog`
#125
rachitnigam
closed
2 years ago
2
Examples missing `#pragma main`
#124
rachitnigam
closed
2 years ago
4
Allow global variables to be top level inputs or outputs
#123
JulianKemmerer
opened
2 years ago
0
Clock enables / feedback inputs do not work as expected for autopipelined logic
#122
JulianKemmerer
opened
2 years ago
5
Detect RAMs from static arrays
#121
JulianKemmerer
closed
2 weeks ago
2
Create PipelineC demo using Sabana
#120
JulianKemmerer
closed
2 weeks ago
0
Improve implementation of debug port wires
#119
JulianKemmerer
closed
2 years ago
2
How to combine multiple clock domains in a single function?
#118
JulianKemmerer
closed
2 weeks ago
0
Explore Reticle IR support
#117
JulianKemmerer
closed
2 weeks ago
0
Pretty self explanatory
#116
ghost
closed
2 years ago
0
added smoke test + contributor doc info + Black
#115
ghost
closed
2 years ago
1
Changing the top level module name
#114
barbossa404
closed
2 years ago
1
Language wide simulation test case support
#113
JulianKemmerer
closed
2 weeks ago
0
Import fixes/spring cleaning
#112
ghost
closed
2 years ago
2
removed cruft (mostly commented out code)
#111
ghost
closed
2 years ago
0
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