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efabless
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caravel_mgmt_soc_litex
https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
Apache License 2.0
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VexRISCV core missing WFI
#36
tbialas-riverlane
opened
2 years ago
0
fix issue_34
#35
suppamax
opened
2 years ago
0
[Litex] "make setup" generates the signal list twice
#34
suppamax
opened
2 years ago
0
Wishbone test
#33
suppamax
opened
2 years ago
2
add instructions to README.md on how to run tests
#32
mattvenn
opened
2 years ago
2
extended irq test
#31
suppamax
opened
2 years ago
0
env.makefile should use MCW_ROOT to refer to caravel_mgmt_soc_litex
#30
proppy
opened
2 years ago
0
cleanup hardcoded path in makefiles
#29
proppy
opened
2 years ago
1
verilog/dv/make: fix typo in comments
#28
proppy
opened
2 years ago
0
remove deprecated spi_flash (#26) + wishbone test (#24)
#27
suppamax
closed
2 years ago
2
ImportError: cannot import name 'SpiFlash' from 'litex.soc.cores.spi_flash'
#26
suppamax
opened
2 years ago
0
add a new more comprehensive gpio test
#25
mattvenn
closed
2 years ago
4
add wishbone test
#24
mattvenn
opened
2 years ago
3
add IRQ info to docs
#23
mattvenn
opened
2 years ago
1
user_porject_wrapper not properly included
#22
kareefardi
closed
1 year ago
1
mprj wishbone address range is limited to 0x3010_0000 instead of 0x3fff_ffff
#21
mattvenn
closed
1 year ago
7
Introduction of PDK variable
#20
marwaneltoukhy
closed
2 years ago
0
Include files from user_project
#19
marwaneltoukhy
closed
2 years ago
0
Fix DFFRAM when building non gate level tests
#18
antonblanchard
opened
2 years ago
1
caravel_user_project dv integration with litex
#17
marwaneltoukhy
closed
2 years ago
0
add link to readthedocs on the README.md
#16
mattvenn
opened
2 years ago
0
repo is huge
#15
mattvenn
opened
2 years ago
0
Create LICENSE
#14
jeffdi
closed
2 years ago
0
readthedocs fix
#13
jeffdi
closed
2 years ago
0
Documentation Updates
#12
Manarabdelaty
closed
2 years ago
0
mgmt_core/user_irq input_delay missing?
#11
mbalestrini
opened
2 years ago
2
litex-based mprj wishbone region size is significantly smaller than the previous picorv32-based design
#10
harrisonpham
closed
1 year ago
1
port timer testbench
#9
jeffdi
closed
1 year ago
0
port irq testbench
#8
jeffdi
closed
1 year ago
0
port spi master testbench
#7
jeffdi
closed
1 year ago
0
port uart testbench
#6
jeffdi
closed
1 year ago
0
port test bench for memory
#5
jeffdi
closed
2 years ago
2
port testbench for mgmt gpio from caravel
#4
jeffdi
closed
1 year ago
2
integrate OpenRAM & DFFRAM
#3
jeffdi
closed
2 years ago
1
build mgmt soc matching caravel io definition using Litex
#2
jeffdi
closed
2 years ago
1
Make sure design is able to boot on a Digilent Arty A7 board
#1
mithro
opened
2 years ago
4
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