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efabless
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caravel_mgmt_soc_litex
https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
Apache License 2.0
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Add SoC Lib
#86
passant5
closed
1 year ago
0
add signoff sdc and results
#85
passant5
closed
1 year ago
0
update RAM128 and RAM256
#84
mo-hosni
closed
1 year ago
0
Mgmt core wrapper views
#83
mo-hosni
closed
1 year ago
0
update cocotb netlist
#82
M0stafaRady
closed
1 year ago
0
Unused directory ./lvs
#81
marwaneltoukhy
opened
1 year ago
0
add sdc dir for signoff sdcs
#80
marwaneltoukhy
closed
1 year ago
0
Caravel redesign: mgmt_core_wrapper
#79
mo-hosni
closed
1 year ago
0
Rerhardened mgmt_core_wrapper to reduce antenna violators.
#78
mo-hosni
closed
1 year ago
1
removed all views related to DFFRAM and mgmt_core (old)
#77
marwaneltoukhy
closed
1 year ago
1
updated openlane and open_pdks commit
#76
marwaneltoukhy
closed
1 year ago
0
update mgmt_core_wrapper powered gl.
#75
mo-hosni
closed
1 year ago
0
remove openlane old runs
#74
marwaneltoukhy
closed
1 year ago
0
update DFFRAM names
#73
jeffdi
closed
1 year ago
0
update module names for DFFRAM
#72
jeffdi
closed
1 year ago
0
Update the DFF interface
#71
jeffdi
closed
1 year ago
0
Caravel redesign
#70
mo-hosni
closed
1 year ago
0
Caravel redesign
#69
mo-hosni
closed
1 year ago
1
generated mgmt_soc and dffram cell name and interface mismatch
#68
kareefardi
closed
1 year ago
1
Caravel redesign
#67
mo-hosni
closed
1 year ago
0
Caravel redesign
#66
mo-hosni
closed
1 year ago
0
change 2nd DFFRAM to 512B
#65
jeffdi
closed
1 year ago
0
change 2nd DFFRAM to 512B
#64
jeffdi
closed
1 year ago
0
correct defs.h
#63
jeffdi
closed
1 year ago
1
correct defs.h
#62
jeffdi
closed
1 year ago
0
Added a verification testbench for testing GPIO pull-up and pull-down
#61
RTimothyEdwards
closed
1 year ago
0
create pass-thru ports for clock and resetn
#60
jeffdi
closed
1 year ago
0
Clock reset passthru
#59
jeffdi
closed
1 year ago
0
replace SRAM with DFFRAM
#58
jeffdi
closed
1 year ago
1
replace OpenRam with DFFRAM
#57
jeffdi
closed
1 year ago
1
Added the "constant_block" in the include
#56
RTimothyEdwards
closed
1 year ago
1
Fix pull definitions again
#55
RTimothyEdwards
closed
1 year ago
0
rtl: add clock and reset passing thru mgmt_core_wrapper
#54
kareefardi
closed
1 year ago
0
correct GPIO definitions in caravel.h
#53
jeffdi
closed
1 year ago
3
Different definitions at caravel.h and defs.h
#52
M0stafaRady
closed
1 year ago
3
SRAM second port has "no connect" inputs
#51
RTimothyEdwards
opened
1 year ago
2
UART cannot receive more than 1 character
#50
M0stafaRady
closed
1 year ago
1
new environment for simulation automation with cocotb and vcs
#49
M0stafaRady
closed
1 year ago
3
Wb address fix
#48
jeffdi
closed
1 year ago
0
Fix pull definitions
#47
RTimothyEdwards
closed
1 year ago
2
Triple-repeated statements
#46
jeffdi
closed
1 year ago
3
Correct for missing power supply pins in SRAM and VexRISC core
#45
RTimothyEdwards
closed
1 year ago
1
add gf180mcuC variant
#44
proppy
opened
1 year ago
1
Temp fix use power pins
#43
jeffdi
closed
1 year ago
0
Resource not found: serial:None while building with picorv32
#42
rhit-painteza
opened
1 year ago
0
Added an ifdef for USE_POWER_PINS around the power pins of the SRAM in RTL verilog
#41
RTimothyEdwards
closed
1 year ago
1
'make verify' does not work
#40
RTimothyEdwards
opened
1 year ago
1
In verilog model of standard cells, fix "notifier" register definition
#39
derekcom17
opened
2 years ago
1
Cannot access housekeeping register for SPI and SYS
#38
devsaurus
closed
1 year ago
1
PDK variable fix
#37
marwaneltoukhy
closed
2 years ago
0
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