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Type of issue: feature request
Impact: unknown
Does Chisel compiler or FIRRTL support the conversion or the compilation to System Verilog besides Verilog?
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## Behavior
brew install verible
==> Fetching chipsalliance/verible/verible
==> Cloning https://github.com/chipsalliance/verible.git
Updating /Users/entwinedime/Library/Caches/Homebrew/verible--gi…
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`invalid-system-task-function` states:
> Checks that no forbidden system tasks or functions are used. These consist of the following functions: `$psprintf`, `$random`, and `$dist_*`. As well as non-L…
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Hi, I am looking for that controller in Verilog/system Verilog. Can you help me please?
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Section 10.8 of the system verilog LRM covers labeled statements, and I'd like to try yosys on a project that has code using them. Here's an example of a labeled statement:
```
module test_label_pro…
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The microstrip devices models #94 will be most likely implemented in form of Verilog-A modules. These modules should be compiled with OpenVAF and attached to Ngspice. It's need to provide a way to att…
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TerosHDL:Global output: 2024-06-19 09:53:02.780 [info] [00000.001204] ERROR: Can't guess frontend for input file `d:/workSpace/sim/fifo/axis_async_fifo.v;' (missing -f option)!
When I'm in the CMD wi…
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The CVA6 uses the following defines (used in ifdef/ifndef statements):
- DROMAJO
- FIRESIM_TRACE
- FORMAL
- INSTR_TRACER_IF_SV
- PITON_ARIANE
- SYNTHESIS
- VERILATOR
- WT_DCACHE
Similar t…
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**Describe the bug**
Module instantiation instantiates ports but not parameters.
**Environment (please complete the following information):**
- OS: Win 11
- VS Code version 1.88.0
- Extensio…
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### Describe the bug
The crash occured during string interpolation editing. Not sure how to replicate. Hope this log helps:
```
2024.08.21 20:11:30 ERROR Failed to tokenize input for semantic tok…