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pymtl
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pymtl3
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
BSD 3-Clause "New" or "Revised" License
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support @update_once
#184
jsn1993
closed
4 years ago
1
fix vtbgen reset
#183
jsn1993
closed
4 years ago
0
Improve verilog tbgen pass
#182
jsn1993
closed
4 years ago
1
GC fix & translation performance opt
#181
jsn1993
closed
4 years ago
1
catch reassignment
#180
jsn1993
closed
4 years ago
1
refactor gen signal expr
#179
jsn1993
closed
4 years ago
2
Pytest plugin and a few import improvements
#178
ptpan
closed
4 years ago
2
Finalize Bits semantics & achieve 100% coverage for Bits_test
#177
jsn1993
closed
4 years ago
1
Add more request types to MemMsg
#176
qtt2
closed
4 years ago
2
Add v_libs option
#175
ptpan
closed
4 years ago
1
Fixed amo method in MemIfcFL2CLAdapter
#174
qtt2
closed
4 years ago
4
add case name support
#173
jsn1993
closed
4 years ago
0
Fix the non-determinism in component.get_*
#172
ptpan
closed
4 years ago
1
Fix a bug in boolean temporary variable
#171
ptpan
closed
4 years ago
0
@=
#170
jsn1993
closed
4 years ago
1
Bug fix when translating `-1` literal
#169
ptpan
closed
4 years ago
0
Non-top placeholder Portman
#168
ptpan
closed
4 years ago
0
Verilog TBgen
#167
jsn1993
closed
4 years ago
1
Support random seed through vl_xinit
#166
ptpan
closed
4 years ago
1
Implement pass data APIs
#165
ptpan
closed
4 years ago
1
Better constant extraction during RTLIR generation
#164
ptpan
closed
4 years ago
2
Bug fix in importing parametrized Verilog module
#163
ptpan
closed
4 years ago
1
Translation/import bug fix
#162
ptpan
closed
4 years ago
1
Fix array translation bug
#161
ptpan
closed
4 years ago
0
Fix a translation bug of arrays of components
#160
ptpan
closed
4 years ago
1
Verilog translation bug fix
#159
ptpan
closed
4 years ago
1
Revamp the SystemVerilog backend
#158
ptpan
closed
4 years ago
1
Fix Bits
#157
jsn1993
closed
4 years ago
1
allow line break in lambda
#156
jsn1993
closed
4 years ago
1
Major syntax changes
#155
jsn1993
closed
4 years ago
1
Assertion error in DelayPipeCL
#154
qtt2
closed
4 years ago
0
No-synthesis translation config
#153
ptpan
closed
4 years ago
0
connect_bits2bitstruct
#152
yo96
closed
4 years ago
4
Verilog non-static component and interface translation
#151
ptpan
closed
4 years ago
0
improved debug message for <<= bitwidth mismatchw
#150
mondO
closed
4 years ago
1
Bits call method
#149
JakeStevens
closed
4 years ago
2
Response-Aware Memory Master
#148
JakeStevens
closed
4 years ago
4
Add an api that works at any time to get the type of a signal
#147
jsn1993
closed
11 months ago
1
port my import pass improvements to 5745 branch
#146
jsn1993
closed
4 years ago
1
Improve import pass
#145
jsn1993
closed
4 years ago
1
improve dynamic scheduling
#144
jsn1993
closed
4 years ago
0
Correct the imemresp_q/drop order in tinyrv0
#143
jsn1993
closed
4 years ago
1
adding ascii mode for printwave_pass
#142
kaishuocheng
closed
4 years ago
3
add clone in bitstruct and bits to get rid of deepcopy
#141
jsn1993
closed
4 years ago
1
fixed the _add_component bug
#140
jsn1993
closed
4 years ago
1
No error or warning thrown when using `<<=` in a update block
#139
yo96
closed
11 months ago
3
fix lambda block name when the signal has bracket, add translation tests
#138
jsn1993
closed
4 years ago
4
add print_line_trace, refactor sim_reset
#137
jsn1993
closed
4 years ago
1
Generic method ifcs
#136
jsn1993
closed
4 years ago
3
Enforcing constraints across components
#135
JakeStevens
closed
4 years ago
2
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