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pymtl
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pymtl3
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
BSD 3-Clause "New" or "Revised" License
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[mem] Add out-of-bound detect to behavioral memory
#234
ptpan
closed
2 years ago
0
Verilator 4.228 support
#233
ptpan
closed
2 years ago
0
GitHub Actions: Add Python 3.10 and 3.11 to testing
#232
cclauss
closed
1 year ago
2
get tests running on ProcFL
#231
cbatten
closed
2 years ago
0
ECE4750 2022
#230
ptpan
closed
11 months ago
2
Failed to compile Verilator 4.224
#229
metoofan
closed
2 years ago
1
Fixing subscript error with array of ifcs
#228
ptpan
closed
2 years ago
1
Add default values to cmdline_opts
#227
ptpan
closed
2 years ago
1
Add --test-yosys-verilog to pytest plugin
#226
ptpan
closed
2 years ago
2
Add --dump-textwave option to the pytest plugin
#225
ptpan
closed
2 years ago
1
Add a Resetable RegisterFile to stdlib basic rtl
#224
jbrzozo24
closed
2 years ago
8
[stdlib] fix val/rdy autoconnect
#223
yo96
closed
10 months ago
4
[translation] Move clk/reset connections ahead within ifndef SYNTHESIS
#222
ptpan
closed
2 years ago
2
Add support for changing toplevel module name through macro definition
#221
ptpan
closed
2 years ago
1
Suppress data_too_large warning from hypothesis in datatype tests
#220
ptpan
closed
2 years ago
1
Fix vtb for arrays of vector ports
#219
ptpan
closed
2 years ago
1
Example fails: type object 'NamedObject' has no attribute '_elaborate_stack'
#218
yurivict
closed
2 years ago
1
Add codecov to CI
#217
ptpan
closed
3 years ago
1
Merge changes during ECE5745 2021
#216
jsn1993
closed
3 years ago
2
Add github action for CI
#215
jsn1993
closed
3 years ago
0
Support 3.7, 3.8. 3,9, 3.10 using one copy of codebase
#214
jsn1993
closed
3 years ago
2
[VcdGen] Fix vcdwave in default pass
#213
ptpan
closed
3 years ago
0
bypass queues should now support non-power-of-2 sizes
#212
nfc35
closed
3 years ago
3
[CI] Disable pypy CI job
#211
ptpan
closed
3 years ago
0
Display port name correctly on error in run_test_vector_sim
#210
cbatten
closed
3 years ago
0
[Fix] Honor non-top port maps in subcomp declarations
#209
ptpan
closed
3 years ago
1
Add on-demand VCD support to model config
#208
ptpan
closed
3 years ago
0
On-demand VCD dumping
#207
ptpan
closed
3 years ago
2
Bump cryptography from 3.0 to 3.3.2 in /requirements
#206
dependabot[bot]
closed
3 years ago
1
cryptography pypy workaround
#205
ptpan
closed
3 years ago
1
Always honor explicit_module_name
#204
ptpan
closed
3 years ago
1
save pickled file as string
#203
jsn1993
closed
3 years ago
1
[VTB] Check for X on DUT interface
#202
ptpan
closed
3 years ago
1
tbgen set values during reset
#201
jsn1993
closed
11 months ago
2
Fix out-of-bound index in verilog_cmp
#200
ptpan
closed
4 years ago
1
Fix a placeholder caching issue
#199
ptpan
closed
4 years ago
2
Minor translation and import bug fix
#198
ptpan
closed
4 years ago
1
Slicing non-Bits signals inside update blocks does not generate very helpful error messages
#197
ptpan
closed
11 months ago
1
Implement sequential & combinational ROM
#196
jsn1993
closed
4 years ago
1
Support s.bitstruct_wire //= s.bits_wire
#195
jsn1993
closed
11 months ago
1
Implement add_value_port API and fix verilator bugs and fix formatting tools
#194
jsn1993
closed
4 years ago
1
fix verilator vcd
#193
jsn1993
closed
4 years ago
1
fix component name with struct parameter
#192
jsn1993
closed
4 years ago
0
Assuming other is not Bits?
#191
JimJJewett
closed
4 years ago
3
Use create_req to make AMO request in MemIfcFL2CLAdapter
#190
qtt2
closed
4 years ago
1
disable lambda block ast caching
#189
jsn1993
closed
4 years ago
1
More backend/stdlib fixes
#188
jsn1993
closed
4 years ago
3
Fix dump_vcd
#187
jsn1993
closed
4 years ago
1
official 3.0 release
#186
jsn1993
closed
4 years ago
1
stdlib reorg + passes reorg
#185
jsn1993
closed
4 years ago
1
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