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Incomplete and discrepancy about Caliptra ROM integration requirements.
1. Inconsistencies between:
- Main spec [Figure 8: Caliptra Core block diagram](https://github.com/chipsalliance/Caliptra…
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to increase bandwidth and to to reduce AHB latency
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Hi, I am filling this issue to review couple of Lint issues inside Veer RTL.
1. In **el2_veer.sv** file, below highlighted signals are read but never set.
assign ifu_axi_bready_int …
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Renode supports at the moment the following AMBA protocols:
- APB
- AXI-Lite
- AXI
AHB support is missing at the moment and it will be great if Renode adds support for it.
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### setuptools version
70.0.0
### Python version
Python 3.12
### OS
Mac M2 Pro Max, Mac M1 Pro
### Additional environment information
[metadata]
name = backend
description = backend
author =…
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In Chipyard/generators/Rocket-chip/src/main/scala/SubSystem/Config.scala
In Class WithDefaultMMIOPort, I change the ExtBus => ExtBusAHB
In Chipyard/generators/Rocket-chip/src/main/scala/SubS…
HC-Lo updated
2 years ago
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Hi,
fpga_optimize defaults to 1 and it cannot be set to 0 on the command line (cannot receive a parameter and if not defined will be set to default value 1 !).
If this value shall never be set to 0,…
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Hi,
I am a beginner at integrating the AHB, and want to know how the addr and data width are getting set in
```
@property
def data_width(self):
return self._data_width
…
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*rogerpueyo:*
The ath79/mikrotik MikroTik SXT Lite images (initramfs, sysupgrade) are missing the MikroTik Routerboard platform drivers. Therefore, the hard_config and soft_config partitions are not …
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Hi,
I've checked out you "verilog-axi" repo (which is really cool and contains pretty much all the AXI tools) and I've found a bug in the AXIL crossbar where it doesn't support M_ADDR_WIDTH < 12. …