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## Description
Current version of Yosys_RS is syncronized with Yosys-HQ [0.38 release tag](https://github.com/YosysHQ/yosys/tree/yosys-0.38), Yosys_RS should be syncronized with the latest Yosys-HQ…
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Dear developers,
I faced some problems in the synthesis step:
In the build/hw/syn/yosys
3.141. Executing AST frontend in derive mode using pre-parsed AST for module `\VX_fpu_sqrt'.
Paramete…
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The VTR quick start guide uses Odin II as the synthesis tool, but the yosys/parmys flow is now the default VTR flow. We should update the quick start to use yosys/parmys. The Odin II section should b…
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I am using VHDL and when I try and use the schematic viewer it works fine with entities in their own file but when i create an instance of a entity in another file GHDL fails to find the work lib. Th…
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When Lakeroad is used to synthesize a design with multiple modules, `lakeroad.so` experiences a segmentation fault.
![image](https://github.com/user-attachments/assets/f3e1caaf-022e-4281-a225-98ff…
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Hi, Just recently encountered your paper, and would like to know if the script of yosys processing (into PPIs/ PPOs) can be provided? Thanks for your help!
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### Version
yosys 0.41+126
### On which OS did this happen?
Linux
### Reproduction Steps
Hello,
I encountered a crash issue while using Yosys to synthesize a Verilog file. The specific details…
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### Is there an existing CVA6 bug for this?
- [x] I have searched the existing bug issues
### Bug Description
I am trying to synthesize the CVA6 core using open-source tools. Our synthesis flow inv…
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The YosysOptimizer uses the Verilog Emitter to emit code that can be passed to Yosys, then runs a yosys script. It would be a better practice to directly convert to the RTLIL IR and skip that intermed…