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I'm working with the ice40_hx8k_b_evn. In time to do the "make firmware-connect" the console keeps loading and doesn't respond anymore.
```
~/litex-buildenv $ make firmware-connect
flterm --port=…
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Though running simulations in hardware development is relatively slow compared to software developments, a faster CI could surely save time and encourage more people to contribute and to contribute mo…
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Hi, i am trying Yosys compilation for bitstream following https://fabulous.readthedocs.io/en/latest/FPGA-to-bitstream/Yosys%20compilation.html
with the default Yosys TCL script`$FAB_ROOT/nextpnr/fab…
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This ticket is a follow up issue to https://github.com/pulp-platform/pulpissimo/issues/104. I still have the same issue on a fresh master version of pulpissimo with a recent sdk (followed documentatio…
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**Task** General support for indexed constants.
**Description** http://dev.myhdl.org/tasks/indexed-constants.html
**Complexity estimation** This is probably a hard task. It has multiple facets, as i…
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When nightly regression runs overnight, there is a lint error in the email report. It appears to be consistenlty on zba_rv32gc.
```
regression-wally test
Command used: python regression-wally …
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### Application Name
Vivado
### Category Name
development
### Company
Xillinx
### App URL
https://www.xilinx.com/support/download.html
### Community URL
_No response_
### Icon URL
_No resp…
sprsr updated
3 months ago
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Thank you very much for your fixes on the VHDL syntax !
For your next release, would it be possible to include the following patch to support the VHDL-2008 syntax ?
http://sourceforge.net/p/veditor/t…
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I would like to add an expected failure mechanism to VUnit. An expected failure means the expectation is that the test case fails. Failing the test case will thus be an OK result. if the test case do…
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Vivado cannot find/locate variables from noc_block_pulse_cir_avg.v file. Thus, the simulation window shows all signals as invalid or empty -- no waveform is generated.
open_project project_3.xpr
o…