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Without all the necessary input files it is not possible to use or check the codes of your repository. Please upload the same.
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objcopy can produce verilog output directly from ELF files with "objcopy -O verilog inputfile outputfile".
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There are many unsupported constructs in Verilog that I faced while trying to run a verilog design through Odin. I have created a micro testcase for each of them and they can be found at: https://g…
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Hi~
SpinalHDL language itself has good generalization and maintainability,
But the quality of the verilog code it generates is not high, the maintainability is poor, and it is difficult to meet the…
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### Before start
- [X] I have read the [XiangShan Documents](https://xiangshan-doc.readthedocs.io/zh_CN/latest). 我已经阅读过香山文档。
- [X] I have searched the previous issues and did not find anything releva…
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Is it possible to add support for a verliog style mux in schematic tool?
assign a = b ? c : d ? e : f;
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Hello :wave: Cool project!
I just wanted to ask what is planned for the Verilog generation in the TODO section of the README? I'm a Verilog RTL developer and would be keen to contribute to this pro…
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What steps will reproduce the problem?
1. ./odin_II.exe -V top_UART.v -a sample_arch.xml
2. Run in Icarus Verilog and the verilog file compiles and runs
3.
What is the expected output? What do yo…
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Hello, how could I use your schematic viewer to visualize diagrams of VHDL/Verilog hierarchical entities starting from source files?
Thank you and congratulations on your project.
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I saw there is openlane integration inside the CFU-playground but unable to see any documentation related to it ,how can we achieve ASIC of CFU?
@ShvetankPrakash did some changes but what are steps …