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**Description**
GHDL crashes when running a simulation.
**Expected behaviour**
It should not crash. When running the exact same simulation using QuestaSim, there are no compilation errors, and th…
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
Hi,
I want to use Questa to run simulations on the CVA6 RTL.
To that end I setup th…
0ena updated
7 months ago
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@LarsAsplund and @umarcor, here is the discussion I promised on Gitter.
In their current form, I find the storage data structures for `string_ptr` and `integer_vector_ptr` a bit confusing. I think …
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Updating questasim from 2020.1_1 to 2022.4_2 breakes the test 'tb_uart_lib.tb_uart_rx.test_receives_one_byte':
```
# 73810000 ps - check - ERROR - Got 1110_1110 (238)…
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Does this exist? If it does not how hard would it be to be created.
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**Describe the bug**
The following error(s) are reported for the snippet below: **_Type cannot be used as an expression_ ``vhdl ls``**
It seems to be the LS can't handle consecutively following att…
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I've been trying to set up the verilator workflow with the comments from the recent pull request #740 in a blank VM with Ubuntu 20.04 (until now I was using QuestaSim and the Genesys II). When executi…
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The following code does not compile in iverilog. I believe this is valid systemVerilog code. At least one commercial tool accepts this happily. iverilog seems to be unhappy about the datatype and w…
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Dear all,
When I run the following command, an error occurs.
```
cd hardware
make apply-patches
# Verilate the design
make verilate trace=1
# Run the tests
app=hello_world make simv trace=1
`…
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I believe in line: https://github.com/IObundle/iob-soc/blob/15268f88d9aae7dfc3df2ecdc736a7d23a8aaa6e/submodules/LIB/hardware/simulation/questa.mk#L12
The "define" should be added to compile flags a…