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Design is missing in edif netlist parser. This make is so that the top_level_instance has a hard coded "top" name as opposed to whatever was defined in the original....
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The EDIF code produced by `write_edif` is incorrectly renumbering the bits in multi-bit values.
## Steps to reproduce the issue
1. Write Verilog code such as the following with inputs/output con…
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Hello!
This is not a bug report for this project, rather a question regarding the Atmel fitters which you might have some input on since you probably have been using them a lot more that I have.
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Hi,
I'm using Atmel's fitter for the ATF150x parts, which can be made to generate an EDIF file, which I was hoping to parse with this project.
The first error I received was in regard to the tim…
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Currently Verilog to Routing only support BLIF. BLIF has a whole bunch of limitations, like not supporting names for objects (only nets). No support for parameters, etc.
It would be good to have su…
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## Steps to reproduce the issue
Testcase: [obuft_inference_bug.zip](https://github.com/YosysHQ/yosys/files/4292965/obuft_inference_bug.zip)
`make top.edif` to generate the invalid EDIF.
## Expe…
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When within the editor spawned by `edif` to edit a function, the CPU usage seems to spike and stay at max until one saves and exits the edit session.
```$ apl
______ _ __ _…
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It would be nice to add the parameters into the intermediate representation direction. Currently to do a cross language conversion from EDIF to Verilog or vice versa requires the composer to look at a…
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https://github.com/YosysHQ/yosys
https://www.zhihu.com/question/26742670?sort=created
https://zhuanlan.zhihu.com/p/399378479
- yosys只负责verilog到网表的部分,布线要用[nextpnr](https://github.com/YosysHQ/nextpnr…
cisen updated
2 years ago
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I am hitting a failure at the configure stage. Is this file missing from the git repo or is it an autotools version issue?
As well, attempts to invoke configure with the explicit --apl-source-dir fai…