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I would like to contribute some SV testbenches for some of your blocks, just to master a bit better the SVA concept. Is the use of SV code for testing acceptable to be committed to the repo?
You ma…
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Hi all, I'm trying to simulate the project for VC707 (VC707_gen1x8lf64) using Vivado 2015.4. The Vivado runs on Ubuntu 14.04. However, the simulation has errors as following:
ERROR: [VRFC 10-1342] …
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I get the following error when I run 'make all-vivado' command in Vivado version 2022.2 without any changes made.
```
Time resolution is 1 ps
run -all
core_v_mcu_tb.qspi.mem_access @ …
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We'd like to run all sims all the time, but ideally only re-build images that have changes. How?
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Hi, I am new to vivado, I made some changes to dcache in rocketchip, now I want to run riscv program in simulation to verify if there is any problem with my design, but I got a lot of errors when I tr…
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I would highly recommend using [the edalize library](https://github.com/olofk/edalize) from @olofk to provide an API to various EDA tools like Icarus or Xilinx's Vivado. If used correctly this would p…
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Hi,
I'm trying to adapt some of the https://github.com/pulp-platform/riscv-dbg/ files for my purposes.
In there there is a declaration of a class with a typedef inside:
```
class riscv_dbg #(
…
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Hi everyone,
I have added the latest CVA5 core (found here: https://github.com/openhwgroup/cva5) to `pythondata-cpu-cva5` (replacing the original core contents Litex has in `pythondata-cpu-cva5/pyt…
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Clash:
```haskell
testBench :: Vec 5 (Bit, Bit)
testBench = (repeat @2 x) ++ (x :> repeat @2 x)
where
x = (0, 0)
```
VHDL:
```vhdl
-- Automatically generated VHDL-93
[..]
architec…
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Hi,
I'm trying to build with Vivado 2020.1 and I'm seeing the following error:
```bash
ERROR: [VRFC 10-396] cannot assign a string to an unpacked type [/mnt/hgfs/test/projects/demo/tvip-axi/src/tvi…