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#### Expected Behaviour
If a nand gate is called upon, it should produce the appropriate output based on it's inputs.
#### Current Behaviour
An error occurs while parsing. This is actu…
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### Environment (OS, Python version, PySpice version, simulator)
Debian GNU/Linux 10 (buster)
Python 3.7.3
PySpice version : PySpice master on 20 March 2020 (version 1.3.2)
### Problem statement…
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OriginalInput
```
module AOI (input A, B, C, D, output F);
assign F = ~((A & B) | (C & D));
endmodule
```
Output from test_bison.cpp
```
////////////// test1 ////////////////
VerilogDat…
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Related Issue #848
#### Expected Behaviour
Odin should not need to check the order of ports that are instantiated by name when instantiating a module
#### Current Behaviour
Odin fails with a …
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Related Issue #848
#### Expected Behaviour
Should be able to connect output port to vector element.
If this is not possible, Odin II should at least provide a meaningful error or warning message…
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The intermediate representation is currently not generic. It is tied to EDIF and is unable to handle even some EDIF datastructures. This needs to be fixed.
Steps to fixing this problem:
--Finali…
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Hello @mithro and @eine.
I think that you both know very well the FOSS ecosystem, but I know that you have predilections :P (Verilog and VHDL, of course). Would you check the following categorized …
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New Issue for sst-elements
--------------------------
1 - Detailed description of problem or enhancement
When I want to use Ariel and pintool, the error shows:
FATAL: ArielComponent[arielcpu.cc:…
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**Describe the bug**
After an update, Verilog (`iverilog-unstable`) has compile errors.
**To Reproduce**
Steps to reproduce the behavior:
1. `NIX_PATH=nixpkgs=https://github.com/nixos/nixpkgs/…
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We currently have 48 edif netlists in spydrnet/support_files/EDIF_netlists.
Not all of these will necessarily be readable of Vivado, but for those that are, use vivado to convert them to structural…