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We will probably want to have SRAMs in our design. Memories can be "modeled" in Verilog, but they will get synthesized to a bunch of registers instead of actual memories. Instead, we will need to use …
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The responsibility of this component is to translate between the AHB sub signals that are passed over the AHB to Memory interface determined in #1 to the signals expected by an OpenRAM memory module. …
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I saw you merged a pull request ( https://github.com/bespoke-silicon-group/bsg_fakeram/pull/9 ) which mentions SKY130 but you don't seem to have any example configurations?
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Hi I am trying to run a 16kbyte SRAM on sky130. Is it normal that it will take couple of weeks to generate?
Mine has been running for 1 month now. It generate a temp.gds and I don't see any errors…
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In previous version 8.3.376 `W/L=0.07/0.15` matches newer sources `sky130_sram_1rw1r*.spice`
```
.subckt EL_G3_sky130_fd_bd_sram__openram_dp_cell br1 br0 bl1 bl0 vdd wl1 wl0 gnd a_38_n79#
+ a_400_…
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There are some errors in the LEF file that were fixed in OpenRAM, but have not been ported to AMC.
1) For example, library cells are entirely blocked rather that detailed blockages which will caus…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- [X] Y…
lu0de updated
8 months ago
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**Describe the bug**
A clear and concise description of what the bug is.
While running the compiler for an individual PDK, the compiler could not get the fet libraries or models that has defined o…
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Hi
As per openram documents, the sensing circuit has BL and BL bar which it senses but in reram case there is no BL bar.
I wanted to check if in this open-reram git, are bl and bl bar same and shor…
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From slack channel discussion https://skywater-pdk.slack.com/archives/C017UA7LEUV/p1628746152015600
netgen 1.5.196
During device level LVS comparison, proxy nets are created for unmatched ports.…