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It seems that the iverilog invocation doesn't allow for SystemVerilog support:
https://github.com/google/xls/blob/c330e64365e56439ab9496159aa8664c6cd5eb6a/xls/simulation/simulators/iverilog_simulator…
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It looks like VERILOG_INCLUDE_DIRS is only used for the Modelsim/Questa makefiles and has some usage issues right now. The option +incdir+ separates directories with a "+" between them, and there's no…
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Hi all, I'm trying to simulate the project for VC707 (VC707_gen1x8lf64) using Vivado 2015.4. The Vivado runs on Ubuntu 14.04. However, the simulation has errors as following:
ERROR: [VRFC 10-1342] …
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I'm not sure how no one has brought this up yet, but it seems that something is definitely wrong with the code to recognize and fontify variable names in declarations.
And while I'm here, it would …
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### Version
Yosys 0.39+149
### On which OS did this happen?
Linux
### Reproduction Steps
I inadvertently created a design with a syntax error:
![image](https://github.com/YosysHQ/yosys/assets/5…
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I am getting following error during test bench execution
```
make -C axi_ram/. all
make[1]: Entering directory '/hdd2/verilog-axi/tb/axi_ram'
rm -f results.xml
make -f Makefile results.xml
mak…
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**Defect description:**when we try to work on virtual experiment a blank page is displayed**steps to reproduce the issue:*** click on **iiit hyderabad** under the participating institutes in the vlab…
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It would be very usefull, to add bluesim as simulator, since it compiles the bsv code directly into an executable (bsv → c++ → asm). That increases the simulation speed, which is currently the lar…
Febbe updated
6 months ago
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It would be very nice to do something along the lines of:
```
mymod_v = m.DefineFromVerilogFile("mymod.v")[0]
tester = fault.Tester(mymod_v,mymod.clk)
print(v_tester.peek(mymod_v.internal.))
…
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We'd like to allow both SystemVerilog and VHDL test benches in our project. From #297 I learned that
```python
from vunit import VUnit
```
should be used for VHDL, and
```python
from vunit.veri…