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Hi @MikeOpenHWGroup & @davideschiavone
A new CVFPU [PR](https://github.com/openhwgroup/cvfpu/pull/127) related to implementation tools has been opened.
Even if Synopsys Design Compiler didn't com…
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can you add some common interface stl such like i2c, spi etc?
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- [ ] I'm sure this does not appear in [the issue list of the repository](https://github.com/arco-design/arco-design-vue/issues)
## 基本信息
## 现有案例
现在在做新疆的项目,对维语的支持是必须的
## 预期解决问题
希望支持 维语 并支持 …
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### What problem does this feature solve?
"rtl" languages menus.
i am writing in an "rtl" language and my subMenu is always stuck to the left side of the menu item, which is not suitable for "rtl"…
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### Version
Yosys 0.42+10 (git sha1 7f89a45ad, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
Unzip this folder [uart_issue_yosys.zip](https://…
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While we don't know about good open-source linters for VHDL and SpinalHDL, **(System)Verilog** has got at least three: **Verilator**, **Verible**, **Slang**. Check [this](https://github.com/chili-chip…
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### What
- Ensure the Mobile App works well in Right-To-Left (RTL) languages (such as Arabic or Hebrew)
### Checklist (AI generated)
**Visual Elements & Layout**
- **Text Direction:**
-…
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[Figma designs](https://www.figma.com/file/mXN2bu7ma50VkhqCfUpNie/Microsurveys-Mobile?type=design&node-id=286-15458&mode=design&t=JGeUE2QD6wlvIc19-0)
This is to implement the modal view with the surv…
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When integrating Microblaze with UberDDR3, Vitis throws "Instruction overrun" error after configuring the FPGA. Ideally, the Microblaze fires up and waits at the first breakpoint at start of the progr…
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## `uart_tx` changes with a change in declared IO ports of the module
In this [design](https://github.com/chili-chips-ba/openCologne/tree/main/2.Simple--1--PSRAM), when declaring `logic tick_02us` in…