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Hi,
I did try run a simulation using the following command:
make vcscomp sim USE_SIMULATOR=vcs WAVES=fsdb
But I had the following compile error:
Parsing design file '../master_agent/apb_uv…
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### Version
Yosys 0.45+106 (git sha1 c1228fec2, clang++ 18.1.8 -Og -fPIC -O1 -fno-omit-frame-pointer -fno-optimize-sibling-calls -fsanitize=address)
### On which OS did this happen?
Linux
### Repr…
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Cocotb 1.9.1.
I'm trying to set up a Verilog parameters in a testbench using Python runner.
When using Python runner with Xcelium, it uses -gpg "object_name => value", which according to the …
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Is there an easy way to combine the two tools? Amaranth has simulation support but it would be great to use forastero+cocotb as it's a richer solution. I could just use amaranth to generate verilog an…
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### Problem:
When generating an AXI-lite interface, the internal output interface for a bitfield with `hardware: oa` option, the signal `csr_*_out` is one clock cycle behind `csr_*_waccess`.
This …
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#### Motivation of Refactoring effort
A detailed technical plan can be found at [link](https://docs.google.com/document/d/15m7IbVRbQYLxFQjIVNIZT3VjYDhAqK6cjqCxVuSVDGU/edit?usp=sharing)
The overall…
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### Description
I find myself doing this manual navigation a lot:
![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/708c1923-8f36-4d28-a6ef-55e2291e4b35)
Ideally I cou…
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When Lakeroad is used to synthesize a design with multiple modules, `lakeroad.so` experiences a segmentation fault.
![image](https://github.com/user-attachments/assets/f3e1caaf-022e-4281-a225-98ff…
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**Describe the bug**
I attempted to generate an SRAM instance using the following command:
```
python $OPENRAM_HOME/../sram_compiler.py myconfig.py
```
While some configurations work perfectly, o…
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The Verilog-A model does a manual integration of the filament thickness here:
https://github.com/google/skywater-pdk-libs-sky130_fd_pr_reram/blob/6574676cbbd062d63be0f090013d59ced7302349/cells/rera…