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Are you planning on implementing elaboration as well. Is the ultimate goal to output a synthesizable design? Os is that outside the scope of this project?
> 1364-2005: Elaboration is the process th…
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Hi,
I'm using Atmel's fitter for the ATF150x parts, which can be made to generate an EDIF file, which I was hoping to parse with this project.
The first error I received was in regard to the tim…
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Unsure if this actually applies to the project, as it probably doesn't come up in most (any?) netlists, but Verilog has the concept of primitives, both builtin (`XOR`, `AND`, etc), and [user generated…
agg23 updated
8 months ago
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[Yosys](http://www.clifford.at/yosys/) is currently the de-facto standard implementation for open-source synthesis (we're currently using it along with [nmigen](https://github.com/nmigen/nmigen) to bu…
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Hi,
I have created a circuit schematic in xschem using the sky130 PDK, and am trying to use netgen to generate a ".sim" file from xschem's created ".spice file". The intended purpose of the ".sim"…
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[bert@workstation pcb-plugins]$ make
make all-recursive
make[1]: Entering directory `/home/bert/workspace/git/pcb-plugins'
Making all in src/plugins/
which: no sw_vers in (/usr/lib/qt-3.3/bin:/usr/ke…
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When I try to run either the 'case' or 'assign' examples from the dropdown menu on the website, I get an error `The Verilog code did not produce a valid netlist. `
When I run cello in eclipse usin…
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Yosys can produce EDIF but not read EDIF. It would be nice if EDIF reading support was added to Yosys.
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### Description
Select a data path row, then right click and get a menu to "Show in ..."
![image](https://user-images.githubusercontent.com/2798822/226295495-bf15596b-c2e1-41f1-8a9e-9141fc9f5596.p…
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#### Expected Behaviour
While should be supported. Underneath the supported keywords in the flex it's labelled.
#### Current Behaviour
There's an error that while statements aren't su…