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Hi,
it would be greate to have the support to use string queues within classes (SystemVerilog).
The following example gives `sv_queue_example.sv:6: sorry: SV queues inside classes are not yet supp…
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I have install svlangserver with `npm install -g @imc-trading/svlangserver` and add it to my `coc-setting.json` file:
```
{
"languageserver": {
"svlangserver": {
"comman…
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As for know, Odin doesn't support SystemVerilog. I think of using Verific as frontend tool to parse systemVerilog and even verilog for Odin. I tried to do so and parse the designs using Verific then…
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Hi,
I started used your extension for systemverilog code and for what I could observed some functions on systemverilog are not highlight. I hope you can add these functions to your highlight list. …
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I logged the following issue on BlackParrot, but I want to make sure sv-tests does the right thing when creating the project file.
On SV-Tests, I have the following error (In Surelog) on Blackparro…
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Does it support verilog / systemverilog?
Thanks.
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Latest code can't handle the below syntax:
```
modport Initiator
(
input Clk,
output Address,
output .Dout(DInitiator), // ERROR: syntax error, unexpected '.', expecting TOK_ID
…
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Verilog 2005 specifies that implicit conversion from real to integer should be done by rounding.
yosys does this correctly, however it also generates warnings which cannot be removed (without resorti…
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Currently, the SV source sets only track *.sv files, meaning that a new build won't get triggered if included files get changed.
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The tutorial slides contain (rightfully so) SystemVerilog statements (like `always_comb`). For those statements to be available to yosys, the easiest way is to rename all *.v files to *.sv and adjust …