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@cerna
https://github.com/machinekit/mksocfpga/pull/115/checks?check_run_id=1294764215
AFAIK someone pulled the plug on the old build system a while ago and
someone is yet to place in the replac…
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Hello,
I am working on the lowrisc `frame-buffer` branch and trying to understand how the VGA peripheral works. My initial objective was to increase the VGA resolution, so I started looking at the `p…
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Hi and thanks for attempting to make something useful out of those old Infrant based NAS.
As those SoCs are based on the LEON (v2, v3 ?) 32bit SPARC architecture, i wondered if anyone ever played w…
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This looks like a very interesting project (I develop a VPNish routing software called cjdns which uses salsa20/poly1305) but I was wondering if you had carried out any benchmarks and whether you have…
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Currently, this repo provides a custom systemd service and script (in `examples/passthrough/linux/systemd/`) to load our custom AD1939 and TPA613A2 drivers. This is perfectly functional, but systemd a…
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Hello,
I am currently trying to generate linux image to simulate linux booting on VexRiscv.
To do so, I follows guidelines in src/main/scala/vexriscv/demo/Linux.scala:
```
Buildroot =>
git cl…
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Hi All!
I'm trying to integrate the L2 InclusiveCache from ChipsAlliance (https://github.com/chipsalliance/rocket-chip-inclusive-cache) with a single Rocket core to be used inside the Litex SoC.
…
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Hi wujian100 owners, thanks for your contribution to open the source code of wujian.
But I met some trouble when I want to know more about its architecture or details inside.
Could you release some …
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Hi,
I am trying to build rocket chip for terasic de2115. There are some issues which i think some one with more knowledge on rocket support for de2115 could clarify more and suggest fixes.
I fi…
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if I intergrated nvdla into FPGA successfully , can I just run "nvdla_runtime" to start inference with the FPGA conncted to hostPC ? is this feasible?
Or, is nvdla_sw only designed for simulation ??…