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Currently, the SV source sets only track *.sv files, meaning that a new build won't get triggered if included files get changed.
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Existing code, which synthesises and simulates fine in Xilinx and Synopsys toolchains fails with hdlConverter.
The issue is extraneous commas in module parameter definitions and module instance sig…
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The tutorial slides contain (rightfully so) SystemVerilog statements (like `always_comb`). For those statements to be available to yosys, the easiest way is to rename all *.v files to *.sv and adjust …
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If there is no parameter given to `read_systemverilog`, the error message is strange: it complains that a file `read_systemverilog` can not be read.
## Observed
```
yosys> plugin -i systemverilog…
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I am using svlangserver in Neovim with the default settings.
The linter is Verilator 5.015.
In my projects, the linter emits this error message for all `import`s:
> Importing from missing packa…
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I was trying to use a "mailbox" within my SystemVerilog testbench but got the following error:
../hdl/generator.sv:3: syntax error
../hdl/generator.sv:3: error: mailbox doesn't name a type.
…
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I have very common situations where I convert my file into a supported type, to get decent results with the spell checker:
* SystemVerilog files (.sv and .svh)
* Temporarily change to verilog file…
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It would be nice to have a "parser torture test" for our SV style guide: a synthesizable design which uses all the features we're using in our style guide. We can then use this to quickly check if too…
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Go To Definition work great with VHDL, but don't work with Verilog and SystemVerilog files
- OS: Windows 11
- VSCode version version 1.67.1
![изображение](https://user-images.githubuserconten…
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@phsauter, taken from [here](https://github.com/chili-chips-ba/openCologne/issues/3#issuecomment-2168828088):
> "... we also had a good amount of problems dealing with our (PULP) SystemVerilog, espec…