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Hi
I tried to simulate few axi benchs using xilinx vivado simulator.
I could parse all the code with xvlog succesfuly
But during elaboration I get errors like:
```
$ xelab tb_axi_dw_downsizer
…
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It would be nice if [`test()`](https://github.com/ucb-bar/chisel-testers2/blob/ed8cc043a1e45f01a05fe89541e1f68e9bf3c59f/src/main/scala/chiseltest/ChiselScalatestTester.scala#L121) allowed users to spe…
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I am trying to get my verilog file to dump waves when compiled with iverilog. But when I run tests with the `WAVES=1` env variable I get the following error:
```
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Author Name: **Wilson Snyder** (@wsnyder)
Original Redmine Issue: 955 from https://www.veripool.org
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Reported via email from Alessandro Contreras-Grassi
Please follow up by CCing him.…
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I was debugging #329 and wrote down a simple script for differential testing. Then, I slowly reduced the program to find a minimal program. A few problems that need to be handled (feel free to add mor…
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Hi,
I am not able to get proper instantiation using AUTOINST for submodule with user defined type ports. I have a sub module which has ports defined as user defined type structure. But when I expan…
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Hi, I am playing with the examples from the wiki. The second one (SimpleUnitWithParam) introduces parameters. However it seems that since a commit in 2021 this is somehow broken or the API has changed…
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Hi,
I am using Force() function to force internal signals. But I found it has no effect.
Force() does work for those input signals without HDL drive.
Since force function in systemverilog can for…
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As title.
Issue opened primarily to track commits. May be duplicate of issue #103.
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It is not the first time it happens to me, but last time I was unsure about my sanity. Basically, when I have a debugging issue and set `withWave` or `withFstWave` to get a trace of what's happening, …