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StanfordVLSI
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dragonphy2
Open Source PHY v2
Apache License 2.0
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#179
zamyers
opened
4 months ago
0
Delete unused buildkite pipeline/webhook
#178
steveri
opened
5 months ago
0
Fix adc_thresh - incorrect threshold bitwidth :(
#177
zamyers
opened
1 year ago
0
Add adaptive FFE center tap with sacrificial FFE/ FFE estimation with logic
#176
zamyers
opened
1 year ago
0
Rewrite JTAG in Kratos
#175
zamyers
opened
1 year ago
0
Each PI has its own CDR
#174
zamyers
opened
1 year ago
0
Add AXI interface
#173
zamyers
opened
1 year ago
0
Fix reset logic
#172
zamyers
opened
1 year ago
0
Implement real dependency caching
#171
zamyers
opened
1 year ago
1
Decide how the ADC/ PI should be handled
#170
zamyers
opened
1 year ago
0
Create MM CDR test with frequency difference between TX and RX
#169
zamyers
opened
1 year ago
0
Automate sampling switch alignment
#168
zamyers
opened
1 year ago
0
Verify how the max_sel_mux works
#167
zamyers
opened
1 year ago
0
Create diff channel block for testbench that uses measured channel models
#166
zamyers
opened
1 year ago
0
Fixing Loader Error
#165
zamyers
opened
2 years ago
0
Running Tests link from main StanfordVLSI/DragonPHY2 page
#163
jwrsg
opened
3 years ago
0
Update code coverage metric
#162
sgherbst
opened
3 years ago
0
cvxpy fix
#161
sgherbst
closed
3 years ago
0
Dragonphy ports should all be at top level for proper black boxing.
#160
steveri
opened
3 years ago
1
Phys design v2
#159
zamyers
closed
3 years ago
1
Transmitter hot fix
#158
CansWang
closed
3 years ago
1
Add TX multicycle constraints
#157
sgherbst
closed
3 years ago
1
Phys design v2
#156
zamyers
closed
3 years ago
0
Fix missing output driver information
#155
sgherbst
closed
3 years ago
0
dcore hot fix
#154
sjkim85
closed
3 years ago
3
Constraints update
#153
sgherbst
closed
3 years ago
0
Transmitter
#152
CansWang
closed
3 years ago
0
Transmitter: PDK MUX_n and inverter buffer instantiated, dont_touch is under editing
#151
CansWang
closed
3 years ago
0
Fix TX synthesis bug
#150
sgherbst
closed
3 years ago
0
Fix non-deterministic register map
#149
sgherbst
closed
3 years ago
0
Transmitter
#148
CansWang
closed
3 years ago
4
36 BUFTD4 added as the output stage, dependency problem solved.
#147
CansWang
closed
3 years ago
0
output_buf module create
#146
CansWang
closed
3 years ago
2
cascaded div_b2 in tx_top might fail to operate correctly, asynchronous rst was used.
#145
CansWang
opened
3 years ago
0
Update clock constraints for TX
#144
sgherbst
closed
3 years ago
0
two additional primary IOs for DCORE
#143
sjkim85
closed
3 years ago
2
Physical Design Flow + Datapath Updates
#142
zamyers
closed
3 years ago
4
Combinational loop removed
#141
CansWang
closed
3 years ago
1
Remove combo logic loop in qr_4t1_mux_top
#140
sgherbst
closed
3 years ago
2
Add system-level test of TX, and block-level test of TX data source
#139
sgherbst
closed
3 years ago
0
prbs test & fixed pattern test added!
#138
CansWang
closed
3 years ago
0
Add output buffer (and termination?) for TX
#137
sgherbst
closed
3 years ago
3
Tx block level tests added but not finalized, local prbs test passed
#136
CansWang
closed
3 years ago
4
Add system-level test for transmitter
#135
sgherbst
closed
3 years ago
0
Add block-level test for transmitter
#134
sgherbst
closed
3 years ago
0
Integrate transmitter block
#133
sgherbst
closed
3 years ago
0
Top-level TX integration
#132
sgherbst
closed
3 years ago
0
JTAG register map is not deterministic
#131
sgherbst
closed
3 years ago
2
Remove misc_ctrl_bits register and move PRBS debug I/O to system clock
#130
sgherbst
closed
3 years ago
0
Analog core update
#129
sjkim85
closed
3 years ago
1
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