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StanfordVLSI
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dragonphy2
Open Source PHY v2
Apache License 2.0
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Transmitter
#128
CansWang
closed
3 years ago
0
The transmitter directory created
#127
CansWang
closed
3 years ago
2
Small fixes
#126
sgherbst
closed
3 years ago
4
analog_core updates
#125
sjkim85
closed
3 years ago
6
Fix some block-level tests that were broken under irun/xrun
#124
sgherbst
closed
3 years ago
0
Fix analog_core QTM
#123
sgherbst
closed
3 years ago
0
PFD offset calibration loop updates
#122
sgherbst
closed
3 years ago
0
Mflowgen sgh
#121
zamyers
closed
3 years ago
6
Add features for working with S-parameters
#120
sgherbst
closed
3 years ago
0
Sparam scale is very large
#119
zamyers
closed
3 years ago
2
Sparam File Incompatible for branch s4p
#118
zamyers
closed
3 years ago
2
Move retimer into analog core
#117
sgherbst
closed
3 years ago
1
Add histogram measurement feature
#116
sgherbst
closed
3 years ago
0
Add long-duration histogram capability
#115
sgherbst
closed
3 years ago
0
Add ZCU106 support
#114
sgherbst
closed
3 years ago
0
Get better BER agreement between simulation and emulation
#113
sgherbst
closed
3 years ago
0
Add option for building the emulator with floating-point support
#112
sgherbst
closed
3 years ago
0
Add support for ZCU106
#111
sgherbst
closed
3 years ago
0
Emulator usability updates
#110
sgherbst
closed
3 years ago
1
Add runtime-updatable step response functions
#109
sgherbst
closed
3 years ago
1
Add noise and jitter to emulation models
#108
sgherbst
closed
4 years ago
3
Add higher-performance emulation models
#107
sgherbst
closed
4 years ago
0
Generate "update" signal for adc_unfolding directly, rather than through clock division circuitry
#106
sgherbst
closed
3 years ago
0
Emulation updates
#105
sgherbst
closed
4 years ago
0
Get loopback emulation test working with mixed-signal emulation models
#104
sgherbst
closed
4 years ago
1
Merge emulation and simulation views
#103
sgherbst
closed
4 years ago
0
DRC issue related to unused port of ACORE
#102
sjkim85
opened
4 years ago
1
Test FFE and phase doubling
#101
standanley
closed
4 years ago
2
MM CDR test + other test updates
#100
sgherbst
closed
4 years ago
0
Bug -- en_bypass_ctl only controls PI 0
#99
sgherbst
closed
3 years ago
2
Flatten port names in analog_core + PnR updates
#98
sgherbst
closed
4 years ago
0
Synthesis and pinout updates
#97
sgherbst
closed
4 years ago
1
Analog core5
#96
sjkim85
closed
4 years ago
8
Mflowgen
#95
zamyers
closed
4 years ago
1
Add basic test for MDLL
#94
sgherbst
closed
4 years ago
1
Add integration test for MDLL
#93
sgherbst
closed
4 years ago
1
Add BIST for PRBS checker
#92
sgherbst
closed
4 years ago
0
Set JTAG ID using the git hash
#91
sgherbst
closed
4 years ago
1
Update PRBS, Vcal, mflowgen, JTAG ID
#90
sgherbst
closed
4 years ago
2
Cdr dev
#89
zamyers
closed
4 years ago
2
JTAG Hello Test Correction
#88
zamyers
closed
4 years ago
1
mflowgen updates
#87
sgherbst
closed
4 years ago
2
Analog core2
#86
sjkim85
closed
4 years ago
3
increase coarse delay cell bitwidth from 4 to 5
#85
bclim
closed
4 years ago
1
increase PI bitw from 4 to 5
#84
bclim
closed
4 years ago
3
GDS modification of input buffer
#83
sjkim85
closed
3 years ago
1
Test dev
#82
zamyers
closed
4 years ago
1
Finish MDLL integration
#81
sgherbst
closed
4 years ago
0
Add Mux to push FFE Output into CDR
#80
zamyers
closed
4 years ago
0
Add preliminary top-level synthesis flow
#79
sgherbst
closed
4 years ago
2
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