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StanfordVLSI
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dragonphy2
Open Source PHY v2
Apache License 2.0
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update mdll_r1 jtag interface
#78
bclim
closed
4 years ago
1
Mux ADC output, FFE output, MLSD output into PRBS checker
#77
sgherbst
closed
4 years ago
1
Modify pi_ctl scaling value in DCORE
#76
sjkim85
closed
4 years ago
1
Add pi_ctl valid flag signal to DCORE
#75
sjkim85
closed
4 years ago
2
Analog core2
#74
sjkim85
closed
4 years ago
8
Weight dev
#73
zamyers
closed
4 years ago
3
Add system-level test PRBS test from MLSD output
#72
sgherbst
closed
1 year ago
0
Add system-level PRBS test from FFE output
#71
sgherbst
closed
3 years ago
1
Expand PRBS test to be more of a system-level test
#70
sgherbst
closed
3 years ago
1
Read out data for AC ADC test normally
#69
sgherbst
closed
3 years ago
1
Add system-level test of SRAM memory interface
#68
sgherbst
opened
4 years ago
1
add jtag register map for mdll and update some mdll rtls
#67
bclim
closed
4 years ago
2
Updates from May 1 hackathon
#66
sgherbst
closed
4 years ago
0
Update model parameters for V2T behavioral model
#65
sgherbst
opened
4 years ago
1
Set PI control codes in tests through normal JTAG debug signals
#64
sgherbst
opened
4 years ago
1
Fix X-pessimism in int_Qperi in PI_local_encoder
#63
sgherbst
closed
3 years ago
2
Add method to directly set PI codes
#62
sgherbst
closed
4 years ago
1
synopsys translate_off
#61
sgherbst
closed
4 years ago
3
Where does JTAG fit into the reset sequence?
#60
sgherbst
closed
4 years ago
4
(meta issue) Move over GitHub issues from dragonphy repo
#23
sgherbst
closed
4 years ago
1
Remove clk_cdr and replace with a clock enable signal
#22
sgherbst
closed
3 years ago
1
Review GLITCH test
#21
sgherbst
closed
4 years ago
7
Investigate mode in CDR to limit updates in PI codes to +/-1
#20
sgherbst
closed
3 years ago
0
Update tests to pulse en_v2t on large changes in PI codes
#19
sgherbst
closed
4 years ago
1
Check that en_v2t has a synchronizer
#18
sgherbst
opened
4 years ago
0
Review initial state of pi_ctl_cdr
#17
sgherbst
opened
4 years ago
2
Update reset sequence in testbenches
#16
sgherbst
closed
4 years ago
1
Change en_inbuf default to "0"
#15
sgherbst
closed
4 years ago
1
Integrate mdll in dragonphy_top
#14
sgherbst
closed
4 years ago
2
Add method to trigger ADC dump without external pin
#13
sgherbst
closed
3 years ago
0
Add method to directly set the CTL code of each PI
#12
sgherbst
closed
3 years ago
1
Add AC, AC_REPLICA, and PI_PM tests
#11
sgherbst
closed
4 years ago
1
Add stand-alone test for glitch-free mux
#10
sgherbst
closed
4 years ago
1
initial commit of mdll_r1 rtls
#9
bclim
closed
4 years ago
2
Ext_max_mux_sel creates non-mononicity
#8
zamyers
closed
4 years ago
2
FFE Dev
#7
zamyers
closed
4 years ago
0
ENOB for ADC is low
#6
sgherbst
closed
3 years ago
4
ctl_dcdl_late and ctl_dcdl_early default to zero -- is this expected?
#5
sgherbst
closed
4 years ago
5
mux_gf does not appear to block all glitches
#4
sgherbst
closed
4 years ago
5
Investigate ADC sampling order
#3
sgherbst
closed
3 years ago
2
Analog core2
#2
sjkim85
closed
4 years ago
1
Get PI_PM test working
#1
sgherbst
closed
4 years ago
2
Investigate PI behavior for codes beyond 450
#59
sgherbst
closed
4 years ago
2
Second-pass PRBS checker features
#58
sgherbst
closed
4 years ago
2
Adding tests for new features of analog_core
#57
sjkim85
opened
4 years ago
0
Synthesizable net for inc_delay.sv
#24
sjkim85
closed
4 years ago
1
Add weight update interface
#56
sgherbst
closed
4 years ago
1
Make the JTAG ID include the commit hash and git clean/dirty status bit
#55
sgherbst
closed
4 years ago
1
Add block to convert MLSD output to a bitstream that is compatible with the PRBS checker
#54
sgherbst
closed
1 year ago
2
Check polarity of bypass_inbuf_div
#53
sgherbst
closed
4 years ago
3
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