issues
search
Xilinx
/
RapidWright
Build Customized FPGA Implementations for Vivado
http://www.rapidwright.io
Other
290
stars
108
forks
source link
issues
Newest
Newest
Most commented
Recently updated
Oldest
Least commented
Least recently updated
[DesignTools.deletePblock()]: utility to delete a pblock
#1020
Licheng-Guo
opened
3 months ago
2
[PblockRange]: fix null pointer corner case for BUFG_GT range
#1019
Licheng-Guo
closed
3 months ago
1
Shapes v2, adds tags, fixes issues
#1018
clavin-xlnx
closed
3 months ago
1
[Interchange] Exports DeviceResources Routing (Wires and Nodes) Info in Multiple Messages
#1017
clavin-xlnx
opened
3 months ago
0
flatten netlist with shapes
#1016
zhilix
closed
3 months ago
0
[DesignTools.populateBlackBox()] Fix ConcurrentModificationError
#1015
clavin-xlnx
closed
3 months ago
0
[Interchange] Device Resources Verifier Fixes
#1014
clavin-xlnx
closed
3 months ago
0
Missing properties for DSP48E1?
#1013
yonnorc42
closed
3 months ago
1
2024.1.1
#1012
clavin-xlnx
closed
2 months ago
0
Adding shape support for DREAMPlaceFPGA inputs and Interchange Netlist
#1011
clavin-xlnx
opened
3 months ago
3
Unexpected Laguna Sites Included in `design.getSiteInsts()`
#1010
RipperJ
opened
3 months ago
1
[DesignTools.makeBlackBox()] Fixes an issue of removing CARRY blocks fed by routethrus
#1009
clavin-xlnx
closed
3 months ago
0
Fix null netlist pointer on expanded macro children
#1008
clavin-xlnx
closed
3 months ago
0
Adding HBM ComponentTypes
#1007
clavin-xlnx
closed
3 months ago
0
[EDIFTools] Adding method to create a flat netlist from a hierarchical one
#1006
clavin-xlnx
closed
3 months ago
0
Test for wire/node mismatch reported in #983
#1005
eddieh-xlnx
closed
3 months ago
0
[TestDeviceResources] Test/verify xcau10p
#1004
eddieh-xlnx
opened
3 months ago
0
Node.getAllWiresInNode() returns empty list when Vivado doesn't
#1002
eddieh-xlnx
opened
3 months ago
2
[DeviceResourcesWriter] Output resource timings for US+
#1001
eddieh-xlnx
opened
3 months ago
0
Test for site routing from raw placed design
#1000
clavin-xlnx
closed
2 months ago
0
fix json default value, add out_of_context flag
#999
zhilix
closed
3 months ago
1
Deprecating old usages for Node.getWire()->Node.getWireIndex()
#998
clavin-xlnx
closed
3 months ago
1
2024.1 DCP Write Test
#997
clavin-xlnx
closed
3 months ago
0
disable routability_opt
#996
zhilix
closed
3 months ago
0
Updates to support 2024.1 DCP writing
#995
clavin-xlnx
closed
3 months ago
0
2024.1.0
#994
clavin-xlnx
closed
3 months ago
0
[VivadoTools] Windows fixes
#993
eddieh-xlnx
closed
4 months ago
0
Query on function arguments
#992
nandithaec
opened
4 months ago
3
Running Rapidwright jython through script and eclipse setup issue
#991
nandithaec
opened
5 months ago
2
Add FileTools.getAutoBufferedInputStream() with zstd auto-detect
#990
eddieh-xlnx
closed
5 months ago
0
Discrepancy between RapidWright's pblock.getAllSites with Vivado TCL
#989
RipperJ
closed
5 months ago
1
[DesignTools] Fix NPE in calculateUtilization()
#988
clavin-xlnx
closed
4 months ago
1
BlockPlacer2: Fix off by one error in selecting module instance to move
#987
jakobwenzel
closed
5 months ago
0
Alveo U250 DSP48E2_{X28|X29} cell: <LOCKED>(BEL: (unplaced))
#986
RipperJ
closed
5 months ago
2
How to convert the intermediate result of vpr into a dcp file?
#985
the-centry
opened
5 months ago
3
Updated devices to fix Wire->Node issue
#984
clavin-xlnx
closed
3 months ago
0
xcvh1782 wire/node mismatch
#983
codepilot
closed
3 months ago
5
Fix PolynomialGenerator and TestDCPSave tests
#982
eddieh-xlnx
closed
6 months ago
0
[LaunchTestsOnLsf] Use exit code 1 if any LSF job failed
#981
eddieh-xlnx
closed
6 months ago
0
Add explicit use case for a Jython script in --help
#980
clavin-xlnx
closed
6 months ago
0
[RWRoute] Fix logical driver flag setting for DCP write
#979
clavin-xlnx
closed
6 months ago
1
Remove some pre-2023.2.2 workarounds
#978
eddieh-xlnx
closed
6 months ago
0
Use new Cell.{LOCKED,PORT_TYPE,isPortCell()}
#977
eddieh-xlnx
closed
6 months ago
0
[RWRoute] Consider all nets for timing-driven routing
#976
eddieh-xlnx
closed
6 months ago
0
[VivadoTools] Add placeDesign() and getWorstSetupSlack()
#975
eddieh-xlnx
closed
6 months ago
0
2023.2.2
#974
clavin-xlnx
closed
6 months ago
0
[RWRoute,PhysNetlistReader] Set logical driver on PIPs
#973
eddieh-xlnx
closed
6 months ago
0
[SLRCrosserGenerator] Adds North/South parameterizable bus widths; some error checking
#972
clavin-xlnx
closed
6 months ago
0
[DesignTools.makeBlackBox()] Fix for #967
#970
clavin-xlnx
closed
6 months ago
0
Work around for multi-inverter BEL in DSP58
#969
clavin-xlnx
closed
6 months ago
0
Previous
Next