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enjoy-digital
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litepcie
Small footprint and configurable PCIe core
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how to generate the rtl code of crossbar and dma related .py
#137
constant007
opened
1 week ago
0
Gen4 rework
#136
enjoy-digital
closed
2 months ago
0
phy/usppciephy: Use double wide axis for gen4
#135
Johnsel
closed
2 months ago
5
software/kernel/liteuart: fix linux/of_platform.h no longer including…
#134
Johnsel
closed
2 months ago
0
SIGKILL when doing a dma_test with zero-copy?
#133
sthornington
opened
2 months ago
0
Fix small copypasta in readme - s/liteeth/litepcie
#132
timkpaine
closed
3 months ago
1
The tlast signal doesn't seem to be working
#131
black-pigeon
opened
3 months ago
0
Add DMA Channels dict support to litepcie_gen.
#130
enjoy-digital
closed
4 months ago
0
Expanding spiflash functionality in c++ driver with I2C bitbang and SPIMaster functions
#129
Johnsel
closed
5 months ago
6
PCIe on UltraScalePlus with 256 bit width is broken
#128
smunaut
closed
5 months ago
4
US(P) : Fix x8 / 256 bit wide case
#127
smunaut
closed
5 months ago
3
phy/usppciephy,uspciephy: Disable straddle mode for request completion
#126
smunaut
closed
5 months ago
1
DMAReader not working after update to 2023.12
#125
smunaut
closed
5 months ago
8
litepcie/software/kernel: updated main.c to support Linux kernel 6.5
#124
Johnsel
closed
5 months ago
2
Cleanup Xilinx US/USP PHY integration.
#123
enjoy-digital
closed
8 months ago
0
[Feature request] Implementation of a Root Complex
#122
ohault
opened
11 months ago
1
Add Configuration and PTM TLP support.
#121
enjoy-digital
closed
11 months ago
0
DMA prog mode status register race condition / early-update
#120
smunaut
closed
6 months ago
2
MSI stalls on Ultrascale+
#119
smunaut
closed
12 months ago
2
Added DMA_ADDR_WIDTH constant to kc705.py bench to fix kernel driver
#118
Johnsel
closed
12 months ago
1
Implementing a versatile PCIe switch using LitePCIe
#117
ohault
closed
6 months ago
1
dma_test with external loopback
#116
vbuitvydas
opened
1 year ago
1
[NiteFury] Device not enumerating with x1 x2
#115
luigifcruz
closed
6 months ago
4
add manifest, uplift setup.py to pass twine checks
#114
timkpaine
closed
1 year ago
1
Problems with inter clock timing
#113
cklarhorst
opened
1 year ago
0
No Rx TLP with s7pciephy
#112
xdev-x
opened
1 year ago
0
Xilinx S7: Remove generated verilog dependency.
#111
enjoy-digital
closed
1 year ago
0
Support of Non-Transparent Bridge (NTB) for inter-domain communication through PCIe interfaces.
#110
ohault
closed
6 months ago
3
Compute Express Link (CXL) support
#109
ohault
closed
6 months ago
2
set `DMA_BIT_MASK` to `DMA_ADDR_WIDTH`
#108
sjkelly
closed
1 year ago
1
init Nvidia RDMA/ PCIe P2P Support
#107
sjkelly
opened
1 year ago
0
litepcie/software/kernel/main.c: fix build with kernel >= 5.18 (pci_set_dma_mask -> dma_set_mask)
#106
trabucayre
closed
1 year ago
3
Clarify comments about LitePCIeDMASynchronizer
#105
sjkelly
closed
1 year ago
1
CrossClockDomain FIFO depth too shallow causes inefficiencies
#104
smunaut
closed
1 year ago
1
Is it ASIC proven?
#103
hossamfadeel
closed
1 year ago
1
flawed DMA driver
#102
1n3o1
closed
1 year ago
1
there is no packet separation capability for dma
#101
1n3o1
closed
1 year ago
3
litecpie dma test result in error
#100
1n3o1
closed
1 year ago
3
kernel build result in error
#99
1n3o1
closed
1 year ago
3
clock domain separation of litepcie
#98
1n3o1
closed
1 year ago
2
DMA tlast and tkeep missing
#97
1n3o1
closed
1 year ago
1
Dynamic tlp packetizer switch
#96
enjoy-digital
closed
2 years ago
0
Device Disconnection while `litex_term` is running hangs the kernel over thunderbolt bridge
#95
sjkelly
opened
2 years ago
0
Add PCIe <-> Wishbone function?
#94
tongchen126
opened
2 years ago
1
Add intiial 64-bit addressing support for Bus Mastering (Only for 64-bit datapath for now).
#93
enjoy-digital
closed
2 years ago
0
ltssm_tracer: Fix to register name after integration cleanup
#92
smunaut
closed
2 years ago
1
phy: Add optional LTSSMDebug module
#91
smunaut
closed
2 years ago
2
USP PCIe x8 dma_test hanging
#90
smunaut
closed
2 years ago
5
phy: Add detailled status for UltraScale Plus PCIe PHY
#89
smunaut
closed
2 years ago
1
PCIe issues on ADRV2CRR-FMC
#88
smunaut
closed
1 year ago
3
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