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RTL, Cmodel, and testbench for NVDLA
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change 'spec' file doesn't change RTL code
#172
terencebetter
closed
6 years ago
9
Does nvdla support object detection
#171
Adithyak1998
closed
6 years ago
3
Verilator, "cc_alexnet_conv5_relu5_int16_dtest_cvsram" test failed
#170
terencebetter
opened
6 years ago
3
Clarification needed about external RAM size nv_small
#169
Y159753
opened
6 years ago
3
Question: Why implementation scheme of NV_NVDLA_CDMA_WG_fifo differs from others?
#168
ghost
closed
6 years ago
2
nv_small sdp_3x3x32_ew_lo_lin_int8 testcase failed
#167
kouzhentao
opened
6 years ago
3
Is the file not incomplete, located outdir\nvdla\sdp\NV_NVDLA_SDP_CORE_Y_lut.v ?
#166
xivisi
closed
6 years ago
1
concurrent assignment to non-net signal in NV_NVDLA_CDMA_dc module
#165
JunningWu
closed
6 years ago
1
Function error at outdir/nv_small/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_cvt_top.v
#164
xivisi
closed
6 years ago
1
Syntax error at outdir/nv_small/vmod/vlibs/NV_DW_lsd.v
#163
xivisi
closed
6 years ago
1
About function description of Hardware Architectural
#162
a91102093
opened
6 years ago
2
Master
#161
gowthar
closed
6 years ago
0
Hardware Architectural Specification about registers?
#160
wxbbuaa2011
opened
6 years ago
2
Missing modules during synthesis in CMAC
#159
Y159753
closed
6 years ago
4
Error when build verif_trace_pleyer
#158
dai-pch
opened
6 years ago
4
How to use cmod code for simulation
#157
wxbbuaa2011
opened
6 years ago
4
error while executing the command: tools/bin/tmake -build cmod_top
#156
Adithyak1998
closed
6 years ago
2
Merge pull request #1 from nvdla/master
#155
shjgiser
closed
6 years ago
0
error when execute ./tools/bin/tmake -build vmod for nv_small configuration in Master branch
#154
xranger
opened
6 years ago
1
Integration of DIGITS with NVDLA
#153
Adithyak1998
opened
6 years ago
1
nv_full.spec can't recognized by gcc when use ./tools/bin/tmake vmod to generate RTL.
#152
LeXiaoCCNU
opened
6 years ago
2
add changes required for successful Vivado 2017.4 synthesis (nv_small only)
#151
ghost
closed
6 years ago
10
Master
#150
vijaymails56
closed
6 years ago
1
NOCIF_dram vs NOCIF_sram
#149
elliski
opened
6 years ago
2
Sim Makefile Path Not Found
#148
silvaurus
opened
6 years ago
2
New type of Synthesis error
#147
Y159753
closed
6 years ago
2
Verilator cannot be used for master branch
#146
liuhengibm
opened
6 years ago
7
In nv_large even tested?
#145
elliski
opened
6 years ago
1
Fail to generate vmod
#144
yankanghong
closed
6 years ago
4
Using Questasim instead of VCS
#143
Y159753
opened
6 years ago
13
Winograd in nv_large INT8 version2
#142
elliski
opened
6 years ago
0
RTL Simulation Waveform
#141
silvaurus
opened
6 years ago
2
Support for mixed data type
#140
teabun
opened
6 years ago
0
Where to find detailed description of programming model
#139
teabun
opened
6 years ago
5
Is there a FPGA platform that can be directly used?
#138
liuhengibm
opened
6 years ago
1
Problem about the testbench
#137
NC-Lin-bo
opened
6 years ago
5
Question On CMAC Input Shadowing
#136
silvaurus
opened
6 years ago
2
How to Include DesignWare IPs In Synthesis
#135
silvaurus
closed
6 years ago
3
Function difference between nvdlav1 and master branch (hardware and software)
#134
stevewch
opened
6 years ago
1
Neural Net integrations open questions
#133
Y159753
opened
6 years ago
2
Problem on build lower cost HW
#132
ewq7899987
closed
6 years ago
1
tools/bin/tmake -build cmod_top - can't build cmod_top
#131
darrenleong
opened
6 years ago
11
Silicon Cell Area include Rams in vmod or not?
#130
wyxsky
opened
6 years ago
0
csb_master: add missing 'valid' in core_resp_pvld
#129
ghost
closed
6 years ago
2
Synthesis: Any guidance on setting up SGE?
#128
silvaurus
closed
6 years ago
3
nv_small build issue
#127
thefpgaguy
closed
6 years ago
5
Looking for cdp sanity test
#126
stevewch
opened
6 years ago
1
ram in /model and /synth ??
#125
Y159753
closed
6 years ago
1
Unit conflict found about cap unit
#124
JunningWu
closed
6 years ago
4
Problem RAM generation for synthesis
#123
Y159753
closed
6 years ago
0
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