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openhwgroup
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cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
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Disable MISA WE in Reference Model
#2181
MarioOpenHWGroup
closed
1 month ago
5
add Unprivileged RISC-V ISA for CV32A65X doc
#2180
ASintzoff
closed
1 month ago
0
OBI protocol between Frontend to icache
#2179
yanicasa
closed
4 weeks ago
3
Add support for cv32a65x dedicated synthesis
#2178
Gchauvon
closed
1 month ago
6
doc cv32a65x: update xPELP fields in mstatus
#2177
ASintzoff
closed
1 month ago
0
HOTFIX [riscv-config]: Regenerate output files for CV32A65X.
#2176
zchamski
closed
1 month ago
0
CORE-DV : Merge all exception handlers in one to optimize time simulation
#2175
AyoubJalali
closed
1 month ago
1
Ignore instr_addr_misaligned exception only when also there's a trap
#2174
AyoubJalali
closed
1 month ago
1
refac: (in hpdcache interface) separate the modules for dcache and icache
#2173
takeshiho0531
closed
3 weeks ago
14
[BUG] Spike unknown version issue
#2172
shreyas-kalikar
closed
1 month ago
5
CONTRIBUTING.md does not mention linting
#2171
jquevremont
closed
1 month ago
3
32 bits WB cache
#2170
cyprienh
closed
1 month ago
2
update riscv-isa-manual to riscv-isa-release-1bec7d3-2024-05-28
#2169
ASintzoff
closed
1 month ago
1
Revert "Functional coverage report in CI (#2127)"
#2168
cathales
closed
1 month ago
1
TRAP VERIF : Add checking pc after a trap and remove unnecessary coverage
#2167
AyoubJalali
closed
1 month ago
1
Continue parametrization
#2166
JeanRochCoulon
closed
1 month ago
2
[riscv-config] Fix issues in CV32A65X input spec and regenerate output.
#2165
zchamski
closed
1 month ago
1
Give information on how to clean-up Spike before build
#2164
JeanRochCoulon
closed
1 month ago
1
gen_from_riscv_config utils.py: format and fix typos
#2163
ASintzoff
closed
1 month ago
0
Insert CSR generated from riscv-config in Design Document
#2162
JeanRochCoulon
closed
1 month ago
0
Complete the CSR documentation
#2161
JeanRochCoulon
closed
1 month ago
6
Move spike.yaml to riscv-config directory
#2160
JeanRochCoulon
closed
1 month ago
4
fix gcc-14 compile error on dhrystone: implicit-function-declaration, implicit-int
#2159
xiaoweish
closed
1 month ago
0
Bump verif/core-v-verif from `4e6e860` to `399438e`
#2158
dependabot[bot]
closed
1 month ago
1
Bump core/cache_subsystem/hpdcache from `57c82d3` to `32407cb`
#2157
dependabot[bot]
closed
1 month ago
1
add gen from riscv config software
#2156
AbdessamiiOukalrazqou
closed
1 month ago
0
Update the specification after the last commits
#2155
JeanRochCoulon
closed
1 month ago
1
add gen from riscv config software
#2154
AbdessamiiOukalrazqou
closed
1 month ago
2
[UVM TB] Initialize information about DRAM presence, address and size.
#2153
zchamski
closed
1 month ago
1
Remove redundant tests between 64bits target from smoke-tests
#2152
JeanRochCoulon
closed
1 month ago
2
Updated tb_wb_dcache and adapted it for 32-bits
#2151
cyprienh
closed
1 month ago
0
ADD RISC-V CONFIG SOFTWARE
#2150
AbdessamiiOukalrazqou
closed
1 month ago
5
New target with MMU: cv64a6_mmu
#2149
slgth
closed
1 month ago
2
Update PMA description for CV32A65X
#2148
JeanRochCoulon
closed
1 month ago
1
Add SPP, SIE, SPIE, MXR and SUM description when S-mode is not implemented.
#2147
JeanRochCoulon
closed
1 month ago
0
Update testlist yaml with #2073 PR using yaml anchor/alias
#2146
xiaoweish
closed
1 month ago
4
Two minor simulation flow enhancements
#2145
xiaoweish
closed
1 month ago
1
Disable warnings in Code coverage Job
#2144
AyoubJalali
closed
1 month ago
1
[BUG] Cacheable regions PMA attribute not compatible with AXI memory type signal
#2143
abdelhak-chkirid
opened
1 month ago
0
Fix bug when killing WB cache request
#2142
cyprienh
closed
1 month ago
4
Continue parametrization: as two localparams are not more used by UVM, remove them
#2141
JeanRochCoulon
closed
1 month ago
1
Fix issue #2027
#2140
AyoubJalali
closed
1 month ago
1
HOTFIX: update HVP & CC report script to solve an error in CC job
#2139
AyoubJalali
closed
1 month ago
1
Set env_cfg directly from the CVA6 configuration.
#2138
AEzzejjari
closed
1 month ago
1
Fix issue #2027 Remove localparam
#2137
AyoubJalali
closed
1 month ago
1
[BUG] Cadence Xcelium dependent checksum verilog_package doesn't match
#2136
yunuseryilmaz18
opened
1 month ago
3
[CI] Fix spike version checks on the CVA6
#2135
zchamski
closed
1 month ago
1
Functional coverage : Fix config values in sanity check
#2134
AyoubJalali
closed
1 month ago
1
Add initial riscv-config input specs, validation harness and YAML outputs for CV32A65X.
#2133
zchamski
closed
1 month ago
0
[HOT FIX] Fix csr tests timeout
#2132
AyoubJalali
closed
1 month ago
1
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