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openhwgroup
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cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
https://docs.openhwgroup.org/projects/cva6-user-manual/
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superscalar: do not issue CSR with another instruction
#2329
cathales
closed
3 months ago
1
Page not found for "build prerequisites" and "the toolchain itself" in README
#2328
Tanishqgithub
closed
3 months ago
2
Update number of PMP regions
#2327
JeanRochCoulon
closed
2 months ago
3
[BUG] : pmpcfg1 only right on the lower byte
#2326
AyoubJalali
closed
3 months ago
2
Retry FPGA boot in CI when failed
#2325
valentinThomazic
closed
3 months ago
0
Add CV64A6_MMU core in user manual
#2324
LQUA
closed
2 months ago
2
update riscv-isa-manual to riscv-isa-release-ebf2e3a0b-2024-07-03
#2323
ASintzoff
closed
3 months ago
0
superscalar: make SuperscalarEn a CVA6Cfg attribute
#2322
cathales
closed
3 months ago
1
[BUG] How to verify the output of an addi instruction?
#2321
ais77
closed
2 months ago
6
New toolchain builder script for GCC and LLVM
#2320
math-gout
closed
3 months ago
1
Unable to synthesize using Yosys
#2319
Harshitha276
opened
3 months ago
10
Fix issue #2479 #2468
#2318
AyoubJalali
closed
3 months ago
2
[TASK] Upgrade Spike tandem with DPI functions to access CSRs and to update with Interrupt/Debug signals
#2317
AnouarZajni
opened
3 months ago
3
Add lambda function to sort lint summary according to severity
#2316
Asmaa-Kassimi
closed
3 months ago
1
Add RISCV documentation for cv64a6_mmu
#2315
LQUA
closed
3 months ago
1
feat: update cva6_hpdcache_icache_if_adapter (support continuous virtual address requests)
#2314
takeshiho0531
closed
1 month ago
5
Fix benchmark.sh with correct GCC options and order (Fix #2250)
#2313
Gchauvon
closed
3 months ago
3
refac: cva6 icache fsm hit
#2312
takeshiho0531
closed
2 months ago
10
refac: cva6 icache fsm hit
#2311
takeshiho0531
closed
3 months ago
0
condition csr_regfile.sv
#2310
Asmaa-Kassimi
closed
3 months ago
4
add UVM interrupt agent
#2309
AyoubJalali
closed
3 months ago
5
Genesys 2 UART port disables on connect
#2308
benlarsendk
closed
1 month ago
1
Add illegal instruction to cover corner case in decoder
#2307
AyoubJalali
closed
3 months ago
1
fix lint errors in csr_regfile.sv
#2306
Asmaa-Kassimi
closed
3 months ago
1
Bump verif/core-v-verif from `0e97e74` to `4531071`
#2305
dependabot[bot]
closed
3 months ago
1
[Spike Yaml] Integrate Spike Yaml support.
#2304
zchamski
closed
2 months ago
9
superscalar add second ALU
#2303
cathales
closed
3 months ago
1
Bump CVV to fix issue 2484
#2302
AyoubJalali
closed
3 months ago
2
Bump CVV to use improved scoreboard reporting in tandem simulations.
#2301
zchamski
closed
3 months ago
1
Fix typo on Bitmanip comment
#2300
Gchauvon
closed
3 months ago
0
update expected area
#2299
cathales
closed
3 months ago
1
[BUG] Linking error: undefined reference to htif_t::load_payload
#2298
shreyas-kalikar
opened
3 months ago
3
[BUG] `minstret` and `mcycle` do not increment in debug mode, while `dcsr.stopcount` is set to 0 (normal mode)
#2297
xiaoweish
opened
3 months ago
5
CI: Fix riscv-isa-sim builds
#2296
MarioOpenHWGroup
closed
3 months ago
0
Update uvml_mem use for core-v-verif's PR: 2480/2481/2482
#2295
xiaoweish
closed
3 months ago
3
Add vcs -full64 compile option back
#2294
xiaoweish
closed
3 months ago
1
Add debug_req UVM agent to UVM TB
#2293
xiaoweish
closed
3 months ago
12
Errors on synthesizing and programming CVA6 on Genesys II
#2292
benlarsendk
closed
3 months ago
1
Bump core/cache_subsystem/hpdcache from `25ffa34` to `27f069b`
#2291
dependabot[bot]
closed
2 months ago
3
Error while running riscv-arch-test
#2290
abhikutari
closed
1 month ago
2
[BUG] stall_instr_fetch signal in core/id_stage.sv will not be driven if CVA6Cfg.RVZCMP is disabled
#2289
ckf104
opened
3 months ago
0
just for debugging: Draft extended hpdcache
#2288
takeshiho0531
closed
1 month ago
29
Makefile : passing the tandem_enable value into UVM testbench
#2287
AyoubJalali
closed
3 months ago
1
[gen_from_riscv_config] add custom-gen.yaml support / fix hyperlinks in csr...
#2286
AbdessamiiOukalrazqou
closed
3 months ago
0
Fix mstatus.mpp in relation to the possible legal values
#2285
JeanRochCoulon
closed
3 months ago
4
Fix WARL behavior of MPP in MSTATUS
#2284
Moschn
closed
3 months ago
0
Fix WARL behavior of MPP
#2283
Moschn
closed
3 months ago
1
decoder.sv: add checks for some B instructions (fix #2276)
#2282
ASintzoff
closed
3 months ago
1
fix lint errors in csr_regfile.sv
#2281
Asmaa-Kassimi
closed
3 months ago
9
[BUG] B extension: incorrect decoding for some instructions in RV32
#2280
ASintzoff
opened
3 months ago
2
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