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Your code is very impressive, but could you please tell me how to generate Verilog files?
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### Is there an existing issue for this?
- [X] I have searched the existing issues
### Describe the bug
Input `pre` is not used in the Verilog code for `DflipFlop`.
```verilog
module Dfliā¦
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Hi,
I am trying to simulate a post-synthesis design using either [Verilator](https://www.veripool.org/verilator/) or [icarus verilog (iVerilog)](https://github.com/steveicarus/iverilog) tools.
Tā¦
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### Version
yosys 0.41+126
### On which OS did this happen?
Linux
### Reproduction Steps
Hello,
I encountered another issue while using Yosys to synthesize a Verilog file. The specific details aā¦
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Hi,
I am search for tree-sitter plugin for verilog/systemverilog. "tree-sitter/tree-sitter-verilog" doesn't work well for highlighting.
I am wondering how to use "tree-sitter-systemverilog" in nviā¦
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### Version
yosys 0.41+126
### On which OS did this happen?
Linux
### Reproduction Steps
Hello,
I encountered a performance issue while using Yosys to synthesize a Verilog file. The specific detā¦
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**Description**
When using the GHDL plugin to yosys, and probably more generally, attributes are not attached to instantiations. This causes (for example) yosys to optimise away instantiated blocks ā¦
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Hi!
I downloaded a prebuilt version of Icarus Verilog because I am working on a restricted machine where I don't have sudo rights. Specifically, I can't write to directories like /bin, /opt, etc.
ā¦
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#### Motivation of Refactoring effort
A detailed technical plan can be found at [link](https://docs.google.com/document/d/15m7IbVRbQYLxFQjIVNIZT3VjYDhAqK6cjqCxVuSVDGU/edit?usp=sharing)
The overallā¦
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Icarus Verilog 0.9.7 not available and the new version is not helpful please help me out
regards