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This is sorta a pet issue of @polybeandip's and I want to put it down as a medium/low priority item!
We have at this point implemented [a number of queue structures in Calyx](https://github.com/cal…
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Up to netgen `1.5.269`, it's possible to call a verilog module from a spice netlist. Here are the results of the verilog cell compare.
```
Class XL_brownout_dig (0): Merged 155 parallel devices.
C…
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This reproduces in 3.480 and I don't see any related code changes in the 3.483 version. Continuous assignments in an interface cause a missing method error for new_contassign which exists on Verilog::…
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It seems that portions of Calyx's standard library written in SystemVerilog is not able to be simulated by Icarus.
```sh
[nix-shell:~/Repos/calyx] 11:12:38 $ iverilog -v
Icarus Verilog version 12…
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Addition of a comprehensive top-level verification environment for the design.
The steps to be followed:
1) Make a diagram of this verification environment indicating the placement of components inc…
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Do you have a bit-flipping Verilog?thanks
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Hello, I am running Verilog simulate testbench according to Chapter 17 of the book, but a fault occurred that
```sh
$make run_test
...
cd rv32ui-p-add; echo "Test Result Summary: PASS" +DUMPWAVE…
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In the latest version of trgen, a grammar that has two or more top-level grammars cannot work without specifying in the desc.xml to pick one.
In [glsl](https://github.com/antlr/grammars-v4/tree/a01…
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Hi~
SpinalHDL language itself has good generalization and maintainability,
But the quality of the verilog code it generates is not high, the maintainability is poor, and it is difficult to meet the…
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When running yosys -p "read_verilog -sv generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.sv"
on my newly generated System Verilog code, after finally extending Yosys for the new syntax…