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RoaLogic
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RV12
RISC-V CPU Core
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minstret not counting BEQ
#30
elchanan36
closed
6 months ago
0
Linux compatibility
#29
JOHNTBIJU
opened
3 years ago
2
Debug Control
#28
abdallah250
opened
3 years ago
1
Potential bug with consecutive LOAD instructions
#27
PauliusMorku
closed
2 years ago
7
casex processing
#26
eshellko
closed
2 years ago
1
Design elaboration failed in Xilinx Vivado
#25
kshitij-r
closed
2 years ago
1
Error: rl_ram_1r1w not found in branch prediction unit
#24
neilofranklin
closed
4 years ago
0
Synth Error: Illegal biu_size_t
#23
jeppojeps
opened
5 years ago
2
can't run simulation with vcs
#22
mancomao
opened
5 years ago
0
Update to Privileged1.10
#21
rherveille
closed
6 years ago
0
ICACHE_WAYS = 1 and/or DCACHE_WAYS = 1 fails Xilinx Synthesis
#20
drichmond
closed
2 years ago
3
Reading MCYCLE causes trap
#19
drichmond
closed
6 years ago
1
about the core simulation
#18
youping2009
closed
6 years ago
1
sim: drop Icarus Verilog stuff
#17
frantony
closed
6 years ago
1
docs fixes
#16
frantony
closed
6 years ago
0
can't run simulation with iverilog
#15
frantony
closed
6 years ago
1
Dev/v1.2
#14
sphardy
closed
6 years ago
0
can't find Wishbone stuff in the github RoaLogic/RV12 repo
#13
frantony
closed
6 years ago
2
sim/ahb3lite/regression/bin/Makefile: drop vim's swap file
#12
frantony
closed
6 years ago
1
RV12 Datasheet v1.1 Release
#11
sphardy
closed
7 years ago
4
Initial review
#10
rherveille
closed
7 years ago
0
Documents Update
#9
riscveval
closed
7 years ago
5
Restyle colours for embedding
#8
sphardy
closed
7 years ago
0
Move logo lower
#7
sphardy
closed
7 years ago
0
Update GitHub Pages Configuration
#6
sphardy
closed
7 years ago
0
Documentation
#5
sphardy
closed
7 years ago
0
Documentation
#4
sphardy
closed
7 years ago
0
Update to ReadMe
#3
sphardy
closed
7 years ago
0
Add Non-Commercial License
#2
sphardy
closed
7 years ago
0
Update README.md
#1
sphardy
closed
7 years ago
0