cornell-brg pymtl issues

cornell-brg / pymtl

Python-based hardware modeling framework

BSD 3-Clause "New" or "Revised" License

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issues

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ASIC flow tutorial link is broken

#186 ted-xie closed 3 years ago
1
a small confusion of other language model support

#185 hsqforfun closed 4 years ago
4
Add deprecation note to README

#184 jsn1993 closed 4 years ago
2
possible bug in pclib/ifcs/ValRdyBundle.py

#183 3gx opened 4 years ago
3
pymtl doesn't correctly register combinational blocks that write to slices of an OutPort

#182 Xaec6 closed 4 years ago
2
Various Fixes

#181 orangeturtle739 closed 5 years ago
1
Fix VCD generator

#180 orangeturtle739 closed 5 years ago
2
Slice on fields in bitstruct does not produce valid Verilog

#179 wizard97 opened 5 years ago
0
sext(concat()) does not translate

#178 wizard97 opened 5 years ago
0
Python list slicing translation

#177 wizard97 opened 5 years ago
0
Failed Installation

#176 MattCatz closed 5 years ago
1
[dynamic-ast] Add support for dynamically generated AST

#175 ptpan closed 5 years ago
2
Add a prefix to verilator-xinit comment

#174 jsn1993 closed 5 years ago
7
when use, there is an error list index out of range in metaclasses.py in the floder named model

#173 tristantian closed 5 years ago
8
Fix closures

#172 orangeturtle739 closed 5 years ago
8
Help with design low-level HDL language

#171 XVilka opened 5 years ago
0
add tests for converting model with dynamically generated ast

#170 zhuanhao-wu opened 5 years ago
1
Is it possible to generate sequential blocks in runtime?

#169 zhuanhao-wu opened 5 years ago
15
Use apt-get install flex-old instead of flex

#168 wizard97 closed 5 years ago
6
will pymtl be ported to Python3

#167 CFAndy opened 5 years ago
3
[pymtl/model] Throw friendly error if connect() is called on Model

#166 kkiningh opened 7 years ago
0
Allow empty functions to be elaborated during translation

#165 kkiningh opened 7 years ago
2
Add AST caching to avoid redundant file scan

#164 jsn1993 opened 7 years ago
3
[pclib/rtl] added special case to register file for single read port

#163 gb358 opened 7 years ago
0
pymtl does check ".value" for single level Wire/OutPort but doesn't for the second level within message type

#162 jsn1993 opened 7 years ago
0
Fix Bits-slices value assignment

#161 hawajkm opened 7 years ago
3
Fixed bug in Bits datatype

#160 posadaj opened 7 years ago
3
[perf] Add -O3 to verilation and remove optimization from compilation

#159 jsn1993 closed 7 years ago
0
Fixing translation for sext/zext with sliced value

#158 jsn1993 opened 7 years ago
9
The order of test matters. I think this is a bug

#157 jsn1993 opened 7 years ago
0
The order of test matters if this is correct.

#156 jsn1993 closed 7 years ago
0
Add file lock to support xdist -n options

#155 jsn1993 opened 7 years ago
3
[SC import] Add support for implicit/nested set_port, and additional sourcefolder.

#154 jsn1993 closed 7 years ago
0
explicit_modulename doesn't work for a very simple verilog import

#153 jsn1993 opened 7 years ago
3
[pymtl/tool/integration] SystemC auto import

#152 jsn1993 closed 7 years ago
0
Shall we support implicit include dependency in verilog importing?

#151 jsn1993 closed 8 years ago
5
Cannot wrap a VerilogModel into a pymtl model for simulation

#150 jsn1993 closed 8 years ago
4
Verilator xinit

#149 taylorpritchard closed 8 years ago
4
Fix for collecting arguments in a Model

#148 cbatten closed 8 years ago
3
Verilog translation

#147 Abhinav117 opened 8 years ago
1
Ctorng fixes

#146 ctorng closed 8 years ago
1
Find verilator include dir using pkg-config

#145 jck closed 8 years ago
9
connecting wire slice to wire slice seems not to work

#144 cbatten opened 8 years ago
2
A minor bug (or functional extensions) of range select

#143 jsn1993 opened 8 years ago
0
The link to the research paper in README is wrong

#142 derekchiang opened 8 years ago
2
Verilog Translation Bug: Accessing fields from array of PortBundles not working

#141 stevedai opened 8 years ago
0
PyMTL keywords

#140 ss2783 opened 8 years ago
0
Import/Translation of two identical Verilog models fails

#139 dmlockhart closed 9 years ago
0
Gcd RTL example generates inferred latches

#138 gl387 opened 9 years ago
1
Nested submodule and port list accesses do not translate correctly

#137 dmlockhart opened 9 years ago
0