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efabless
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caravel-gf180mcu
This repository is the GF180MCU port of Caravel. For more information about Caravel, see the original repo at https://github.com/efabless/caravel.
Apache License 2.0
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user_project_wrapper has no liberty file
#144
mo-hosni
opened
1 year ago
3
The template def for caravel_core needs to be generated from chip_io layout
#143
mo-hosni
closed
10 months ago
1
The date in the copyright_block is June 2022 instead of Dec 2022
#142
mo-hosni
closed
1 year ago
1
Metal3 routing obstructions are needed in the area of the power pads connections to the core rings
#141
mo-hosni
closed
1 year ago
1
user_project_wrapper has power pins as data pins
#140
mo-hosni
closed
1 year ago
1
Rerun caravel
#139
mo-hosni
closed
1 year ago
0
Merge from main
#138
mo-hosni
closed
1 year ago
0
Updated the simple_por testbenches
#137
RTimothyEdwards
closed
1 year ago
1
Signals that should not be inputs to buffers are buffered
#136
RTimothyEdwards
opened
1 year ago
1
Corrected chip_io DEF
#135
RTimothyEdwards
closed
1 year ago
0
Fixed the instance naming in gpio_defaults_block views
#134
RTimothyEdwards
closed
1 year ago
0
Regenerated GDS for simple_por for DRC issues
#133
RTimothyEdwards
closed
1 year ago
0
`chip_io` DEF has floating pins
#132
passant5
closed
1 year ago
0
missing subckt in cdls in the pdk
#131
marwaneltoukhy
closed
10 months ago
2
run Antenna check for caravel layout
#130
jeffdi
closed
1 year ago
2
update magic for SRAM & IO extraction
#129
jeffdi
opened
1 year ago
2
review def for chip_io
#128
jeffdi
closed
11 months ago
1
gpio_default layout update
#127
jeffdi
closed
1 year ago
0
fix `chip_io` drive strength signals index issue
#126
passant5
closed
1 year ago
1
adjust nplus/plus overlap of contact in POR layout
#125
jeffdi
closed
1 year ago
0
drive strength control signal not indexing for each IO
#124
jeffdi
closed
1 year ago
0
Fix GL/RTL and DEF mismatches in `chip_io` and `gpio_defaults_block`
#123
passant5
closed
1 year ago
3
Update PoR model timing to depend on the VDD edge
#122
M0stafaRady
closed
1 year ago
0
`gpio_defaults_block` output connections in the layout views don't match the GL/RTL
#121
passant5
closed
1 year ago
0
reharden caravel_core after simple_por update
#120
passant5
closed
1 year ago
0
include SPDX header on RTL
#119
jeffdi
opened
1 year ago
1
Added the GDS for the simple_por
#118
RTimothyEdwards
closed
1 year ago
0
…Corrected the chip_io views for DEF, GDS, and .mag
#117
RTimothyEdwards
closed
1 year ago
0
Redoing these changes after a failed git merge.
#116
RTimothyEdwards
closed
1 year ago
0
More DRCs in Caravel
#115
RTimothyEdwards
closed
1 year ago
1
Corrections for DRC errors
#114
RTimothyEdwards
closed
1 year ago
1
Missing 5V transistor
#113
jeffdi
closed
11 months ago
1
Fix DRCs in caravel
#112
passant5
closed
1 year ago
0
developing timing signoff flow based on StarRCX and Primetime
#111
jeffdi
opened
1 year ago
0
update tapeout scripts based on architecture change (caravel_core vs caravel)
#110
jeffdi
opened
1 year ago
0
run trial tapeout for GF180
#109
jeffdi
opened
1 year ago
0
DRCs in caravel
#108
passant5
closed
1 year ago
0
Added LEF file for the top level
#107
RTimothyEdwards
closed
1 year ago
0
Merge `update_dirs` to `fix_drc`
#106
passant5
closed
1 year ago
0
Update directories `./openlane` and `./verilog/gl`
#105
passant5
closed
1 year ago
1
chip_io LVS transistor level failure
#104
marwaneltoukhy
closed
1 year ago
4
merge main to PnR
#103
passant5
closed
1 year ago
0
Text blocks need to be at origin
#102
RTimothyEdwards
closed
1 year ago
0
Rebased the origin of the various text blocks
#101
RTimothyEdwards
closed
1 year ago
0
POR boot test failed at 500ns delay. (Follow up on why before closing for tapeout.)
#100
azwefabless
closed
1 year ago
4
added stub files
#99
marwaneltoukhy
closed
1 year ago
0
update caravel power routing for the latest `caravel_core`
#98
marwaneltoukhy
closed
1 year ago
0
fixed absolute paths in mag and maglef
#97
marwaneltoukhy
closed
1 year ago
0
updates for simulations
#96
M0stafaRady
closed
1 year ago
0
Caravel redesign
#95
mo-hosni
closed
1 year ago
0
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