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efabless
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caravel-gf180mcu
This repository is the GF180MCU port of Caravel. For more information about Caravel, see the original repo at https://github.com/efabless/caravel.
Apache License 2.0
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Merge changes from main
#94
mo-hosni
closed
1 year ago
0
Caravel core timing iterations
#93
mo-hosni
closed
1 year ago
0
removed old/unused directories/views.
#92
mo-hosni
closed
1 year ago
0
trim metal 5 straps going into user_project_wrapper
#91
jeffdi
closed
1 year ago
1
update `chip_io` gate-level netlist
#90
passant5
closed
1 year ago
0
`chip_io` gate-level netlist has incorrect signal connections
#89
passant5
closed
1 year ago
1
`chip_io` DEF view doesn't match gate-level netlist
#88
passant5
closed
1 year ago
2
SRAM is not LVS clean
#87
marwaneltoukhy
opened
1 year ago
13
remove old/unwanted views
#86
marwaneltoukhy
closed
1 year ago
1
Missing create_top_pins.sh script
#85
RTimothyEdwards
closed
1 year ago
0
Adds the "create_top_pins.sh" script
#84
RTimothyEdwards
closed
1 year ago
2
Metal5 PDN horizontal stripes overlap with the user_project_wrapper PR boundary
#83
mo-hosni
closed
1 year ago
2
gf180mcu caravel redesign
#82
marwaneltoukhy
closed
1 year ago
0
porb does not affect SoC
#81
RTimothyEdwards
closed
1 year ago
1
Merge from main
#80
mo-hosni
closed
1 year ago
0
simple_por is not LVS clean
#79
marwaneltoukhy
closed
1 year ago
2
Modified caravel_clocking to take the "porb" signal as input
#78
RTimothyEdwards
closed
1 year ago
0
Extraction issue in SRAM
#77
marwaneltoukhy
closed
1 year ago
1
Power-on-reset only affects housekeeping
#76
RTimothyEdwards
closed
1 year ago
0
determine strategy for fill generation
#75
jeffdi
opened
1 year ago
0
Merge from main
#74
mo-hosni
closed
1 year ago
0
fixed LVS for housekeeping and mprj_io_buffer
#73
marwaneltoukhy
closed
1 year ago
0
fix `chip_io` incorrect signal connections
#72
passant5
closed
1 year ago
1
`gpio_defaults_block` and `spare_logic_block` DEF views don't match their gate-level netlists
#71
passant5
closed
1 year ago
2
SRAM 512 not DRC clean
#70
marwaneltoukhy
closed
1 year ago
2
Simple POR is not DRC clean
#69
marwaneltoukhy
closed
1 year ago
7
Created gate-level netlists of user_id_programming and gpio_defaults_block
#68
RTimothyEdwards
closed
1 year ago
3
PDN connections to the SRAMs need review.
#67
mo-hosni
closed
1 year ago
0
! generate gpio_defaults_block verilog gl
#66
kareefardi
closed
1 year ago
1
! generate user_id_progamming verilog gl
#65
kareefardi
closed
1 year ago
0
! generate chip_io verilog gl
#64
kareefardi
closed
1 year ago
1
gen_gpio_defaults.py need to be updated for gf180 and the new caravel RTL updates
#63
M0stafaRady
opened
1 year ago
3
power connections of gpio_defaults_block gl are missing
#62
M0stafaRady
closed
1 year ago
1
user_id_programming gl netlist is missing
#61
M0stafaRady
closed
1 year ago
4
Some std cells in the RTL get resized in timing optmizations.
#60
mo-hosni
closed
1 year ago
3
caravel.v instantiates chip_io with signals connected directly to power pins
#59
RTimothyEdwards
closed
1 year ago
1
chip_io incorrect signal connections
#58
RTimothyEdwards
closed
1 year ago
0
gpio_configure registers have incorrect size
#57
M0stafaRady
closed
1 year ago
0
caravel_core is not LVS clean.
#56
mo-hosni
closed
1 year ago
3
Power pads are not connected to the core rings.
#55
mo-hosni
closed
1 year ago
1
chip_io.v gl is missing some ports
#54
mo-hosni
opened
1 year ago
1
merge from main
#53
mo-hosni
closed
1 year ago
0
Adding require changes to run sims
#52
M0stafaRady
closed
1 year ago
0
merge from main
#51
mo-hosni
closed
1 year ago
0
Tristate buffers need to be removed from mgmt_protect.v
#50
RTimothyEdwards
closed
1 year ago
0
Removed the tristate buffers from mgmt_protect.
#49
RTimothyEdwards
closed
1 year ago
0
merge main into PnR
#48
mo-hosni
closed
1 year ago
0
Modified simple_por to make VDD, VSS uppercase
#47
RTimothyEdwards
closed
1 year ago
0
Simple por is not LVS clean
#46
mo-hosni
closed
1 year ago
6
Replace the spare logic macros by spare logic cells
#45
shalan
opened
1 year ago
0
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