laforest Octavo issues - Githubissues

laforest / Octavo

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

http://fpgacpu.ca/

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D write operand may cross over A/B boundaries due to programmed offsets

#65 laforest closed 5 years ago
0
Decode range of addresses for I/O ports

#64 laforest closed 5 years ago
0
Replace "===" with "==" where used for synthesis

#63 laforest closed 8 years ago
0
Pack AOM/BTM bitfields into MLABs initially

#62 laforest closed 5 years ago
0
Re-write and cleanup benchmarks

#61 laforest closed 5 years ago
0
Make a real Assembler

#60 laforest closed 5 years ago
0
Update documentation

#59 laforest closed 5 years ago
0
Check AOM/BTM MLAB usage efficiency

#58 laforest closed 8 years ago
1
Add bit mask or count to AOM to enable modulo addressing and sliding windows

#57 laforest closed 5 years ago
0
Increase AOM address offset range (positive and negative)

#56 laforest closed 5 years ago
0
Increase the number of branch condition flags

#55 laforest closed 5 years ago
0
Use folded CALLs to implement pre-fetching from out-of-core memory.

#54 laforest closed 5 years ago
0
Calculate information in JMP vs. branches

#53 laforest closed 5 years ago
0
Restrict BTM to structured programming support

#52 laforest closed 9 years ago
2
Re-implement RTL conditionals to support proper X propagation

#51 laforest closed 8 years ago
0
Consider hardware/software support for SWAR (SIMD Within A Register)

#50 laforest closed 5 years ago
0
False no-ops and equivalent Boolean operations to hinder power side-channel

#49 laforest closed 5 years ago
0
Use Anull to implement power saving.

#48 laforest closed 5 years ago
0
Detect no-op to raise Annul

#47 laforest closed 5 years ago
0
Re-Align Datapath further down aside Controlpath

#46 laforest closed 5 years ago
1
Move ALU instruction decoding to ID stages

#45 laforest closed 5 years ago
0
Population Count and Count Leading/Trailing Zeros Accelerators

#44 laforest closed 5 years ago
0
Replicate Addressing module per-lane for scatter/gather operation

#43 laforest closed 5 years ago
0
Create efficiency counters

#42 laforest closed 5 years ago
0
Create cycle counters

#41 laforest closed 5 years ago
0
Add loop counters

#40 laforest closed 5 years ago
0
merge wren with data out to update only relevant data I/O register?

#39 laforest closed 8 years ago
1
I/O writes happen one cycle too early!!!

#38 laforest closed 9 years ago
0
Create Double-Move Instruction

#37 laforest closed 5 years ago
2
Turn off useless Quartus warning messages

#36 laforest closed 8 years ago
1
Implement LUT instruction

#35 laforest closed 5 years ago
1
ECC support in Cyclone V

#34 laforest closed 5 years ago
0
Add support for literal pool in Addressing module

#33 laforest closed 5 years ago
0
Factor out pre-DataPath pure pipelines into Spine module

#32 laforest closed 5 years ago
1
Factor I/O Predication out of DataPath

#31 laforest closed 8 years ago
1
Extend D address space +2 bits

#30 laforest closed 9 years ago
1
Place instruction annulling logic in a module

#29 laforest closed 11 years ago
0
Adder between Controller and I_mem is critical path

#28 laforest closed 11 years ago
3
Resource Diversity: Conditional Add and Subtract

#27 laforest closed 5 years ago
0
Create a round-robin mux module to share functional units across cores

#26 laforest closed 5 years ago
0
Add resource diversity option: multiplier (any kind) on I/O ports (or none)

#25 laforest closed 5 years ago
0
Use instruction annulling bit in Controller to re-issue annulled instruction

#24 laforest closed 11 years ago
0
Cancel *all* read and write handshakes if *any* are not ready

#23 laforest closed 11 years ago
0
Annul instruction if the I/O write handshake not ready

#22 laforest closed 11 years ago
0
Annul instruction if any I/O read handshake not ready

#21 laforest closed 11 years ago
0
Convert wren/rden signals to req/ack form

#20 laforest closed 11 years ago
0
Factor out the Memory sub-modules

#19 laforest closed 11 years ago
0
Implement synchronous fork/join/barrier 4-phase handshake modules

#18 laforest closed 5 years ago
0
Port to SystemVerilog

#17 laforest closed 11 years ago
1
Distribute PC fetches across multiple Instruction Memories

#16 laforest closed 5 years ago
0